Timer_A Operation
785
SLAU356I – March 2015 – Revised June 2019
Copyright © 2015–2019, Texas Instruments Incorporated
Timer_A
19.2 Timer_A Operation
The Timer_A module is configured with user software. The setup and operation of Timer_A are discussed
in the following sections.
19.2.1 16-Bit Timer Counter
The 16-bit timer/counter register, TAxR, increments or decrements (depending on mode of operation) with
each rising edge of the clock signal. TAxR can be read or written with software. Additionally, the timer can
generate an interrupt when it overflows.
TAxR may be cleared by setting the TACLR bit. Setting TACLR also clears the clock divider and count
direction for up/down mode.
NOTE:
Modifying Timer_A registers
It is recommended to stop the timer before modifying its operation (with exception of the
interrupt enable, interrupt flag, and TACLR) to avoid errant operating conditions.
When the timer clock is asynchronous to the CPU clock, any read from TAxR should occur
while the timer is not operating or the results may be unpredictable. Alternatively, the timer
may be read multiple times while operating, and a majority vote taken in software to
determine the correct reading. Any write to TAxR takes effect immediately.
19.2.1.1 Clock Source Select and Divider
The timer clock can be sourced from ACLK, SMCLK, or externally from TAxCLK or INCLK. The clock
source is selected with the TASSEL bits. The selected clock source may be passed directly to the timer or
divided by 2, 4, or 8, using the ID bits. The selected clock source can be further divided by 2, 3, 4, 5, 6, 7,
or 8 using the TAIDEX bits. The timer clock divider logic is reset when TACLR is set.
NOTE:
Timer_A dividers
After programming ID or TAIDEX bits, set the TACLR bit. This clears the contents of TAxR
and resets the clock divider logic to a defined state. The clock dividers are implemented as
down counters. Therefore, when the TACLR bit is cleared, the timer clock immediately
begins clocking at the first rising edge of the Timer_A clock source selected with the
TASSEL bits and continues clocking at the divider settings set by the ID and TAIDEX bits.
NOTE:
When the timer is clocked by an external clock, the first two clock pulses are missed due to
internal clock synchronization scheme and the timer starts counting only from the third clock
pulse.
19.2.2 Starting the Timer
The timer may be started or restarted in the following ways:
•
The timer counts when MC > { 0 } and the clock source is active.
•
When the timer mode is either up or up/down, the timer may be stopped by writing 0 to TAxCCR0. The
timer may then be restarted by writing a nonzero value to TAxCCR0. In this scenario, the timer starts
incrementing in the up direction from zero.
