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Debug Peripherals Registers

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SLAU356I – March 2015 – Revised June 2019

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Copyright © 2015–2019, Texas Instruments Incorporated

Cortex-M4F Peripherals

2.5.3.35 TCR Register (Offset = E80h) [reset = 00000000h]

TCR is shown in

and described in

ITM Trace Control Register. Use this register to configure and control ITM transfers. Note 1: You can only
write to this register in privilege mode. Note 2: DWT is not enabled in the ITM block. However, DWT
stimulus entry into the FIFO is controlled by DWTENA. If DWT requires timestamping, the TSSEN bit must
be set.

Figure 2-151. TCR Register

31

30

29

28

27

26

25

24

RESERVED

R/W-0h

23

22

21

20

19

18

17

16

BUSY

ATBID

R/W-0h

R/W-0h

15

14

13

12

11

10

9

8

RESERVED

TSPRESCALE

R/W-0h

R/W-0h

7

6

5

4

3

2

1

0

RESERVED

SWOENA

DWTENA

SYNCENA

TSENA

ITMENA

R/W-0h

R/W-0h

R/W-0h

R/W-0h

R/W-0h

R/W-0h

Table 2-164. TCR Register Field Descriptions

Bit

Field

Type

Reset

Description

31-24

RESERVED

R/W

0h

23

BUSY

R/W

0h

Set when ITM events present and being drained.

22-16

ATBID

R/W

0h

ATB ID for CoreSight system.

15-10

RESERVED

R/W

0h

9-8

TSPRESCALE

R/W

0h

TSPrescale Timestamp prescaler.

0b (R/W) = no prescaling

1b (R/W) = divide by 4

10b (R/W) = divide by 16

11b (R/W) = divide by 64

7-5

RESERVED

R/W

0h

4

SWOENA

R/W

0h

Enables asynchronous clocking of the timestamp counter.

3

DWTENA

R/W

0h

Enables the DWT stimulus.

2

SYNCENA

R/W

0h

Enables sync packets for TPIU.

1

TSENA

R/W

0h

Enables differential timestamps. Differential timestamps are emitted
when a packet is written to the FIFO with a non-zero timestamp
counter, and when the timestamp counter overflows. Timestamps
are emitted during idle times after a fixed number of two million
cycles. This provides a time reference for packets and inter-packet
gaps. If SWOENA (bit [4]) is set, timestamps are triggered by activity
on the internal trace bus only. In this case there is no regular
timestamp output when the ITM is idle.

0

ITMENA

R/W

0h

Enable ITM. This is the master enable, and must be set before ITM
Stimulus and Trace Enable registers can be written.

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Summary of Contents for SimpleLink MSP432P4 Series

Page 1: ...MSP432P4xx SimpleLink Microcontrollers Technical Reference Manual Literature Number SLAU356I March 2015 Revised June 2019...

Page 2: ...61 1 4 3 Behavior of Memory Accesses 61 1 4 4 Software Ordering of Memory Accesses 61 1 4 5 Bit Banding 62 1 4 6 Data Storage 64 1 5 Exception Model 65 1 5 1 Exception States 66 1 5 2 Exception Types...

Page 3: ...ffset 04h 260 3 3 3 RSTCTL_HARDRESET_CLR Register offset 08h 261 3 3 4 RSTCTL_HARDRESET_SET Register offset 0Ch 262 3 3 5 RSTCTL_SOFTRESET_STAT Register offset 10h 263 3 3 6 RSTCTL_SOFTRESET_CLR Regis...

Page 4: ...r offset 0020h 303 4 11 9 SYS_DIO_GLTFLT_CTL Register offset 0030h 304 4 11 10 SYS_SECDATA_UNLOCK Register offset 0040h 305 4 11 11 SYS_MASTER_UNLOCK Register offset 1000h 306 4 11 12 SYS_BOOTOVER_REQ...

Page 5: ...5 11 20 SYS_SRAM_STAT Register offset 0090h 370 5 11 21 SYS_MASTER_UNLOCK Register offset 1000h 371 5 11 22 SYS_BOOTOVER_REQ0 Register offset 1004h 372 5 11 23 SYS_BOOTOVER_REQ1 Register offset 1008h...

Page 6: ...PSSCLRIFG Register offset 3Ch reset 0000h 421 8 Power Control Manager PCM 422 8 1 PCM Introduction 423 8 2 PCM Overview 423 8 3 Core Voltage Regulators 424 8 3 1 DC DC Regulator Care Abouts 424 8 4 P...

Page 7: ...457 9 1 3 Flash Controller Access Privileges 457 9 2 Common Operations Using the Flash Controller 458 9 2 1 Using MSP432 Driver Library for Flash Operations 458 9 2 2 Flash Read 458 9 2 3 Flash Progra...

Page 8: ...ETCH Register offset 00D4h 508 9 4 36 FLCTL_BMRK_DREAD Register offset 00D8h 509 9 4 37 FLCTL_BMRK_CMP Register offset 00DCh 510 9 4 38 FLCTL_IFG Register offset 0F0h 511 9 4 39 FLCTL_IE Register offs...

Page 9: ...Register offset 088h 563 10 4 23 FLCTL_PRGBRST_DATA2_3 Register offset 08Ch 563 10 4 24 FLCTL_PRGBRST_DATA3_0 Register offset 090h 564 10 4 25 FLCTL_PRGBRST_DATA3_1 Register offset 094h 564 10 4 26 FL...

Page 10: ...DEVICE_CFG Register offset 000h 649 11 3 2 DMA_SW_CHTRIG Register offset 004h 650 11 3 3 DMA_CHn_SRCCFG Register offset 010h 4h n n 0 through NUM_DMA_CHANNELS 652 11 3 4 DMA_INT1_SRCCFG Register offse...

Page 11: ...g Controller PMAP 700 13 1 Port Mapping Controller Introduction 701 13 2 Port Mapping Controller Operation 701 13 2 1 Access 701 13 2 2 Mapping 701 13 3 PMAP Registers 704 13 3 1 PMAPKEYID Register of...

Page 12: ...Operation 759 17 2 1 Watchdog Timer Counter WDTCNT 759 17 2 2 Watchdog Mode 759 17 2 3 Interval Timer Mode 759 17 2 4 Watchdog Related Interrupts and Flags 760 17 2 5 Clock Sources of the WDT_A 760 1...

Page 13: ...al Time Clock Calibration for Crystal Offset Error 809 20 2 8 Real Time Clock Compensation for Crystal Temperature Drift 809 20 2 9 Real Time Clock Operation in Low Power Modes 812 20 3 RTC_C Register...

Page 14: ...or 855 22 2 10 Using the Integrated Temperature Sensor 856 22 2 11 Precision ADC Grounding and Noise Considerations 857 22 2 12 Precision ADC Calibration 858 22 2 13 Precision ADC Interrupts 858 22 3...

Page 15: ...ter Format 906 24 3 3 Asynchronous Communication Format 906 24 3 4 Automatic Baud Rate Detection 909 24 3 5 IrDA Encoding and Decoding 910 24 3 6 Automatic Error Detection 911 24 3 7 eUSCI_A Receive E...

Page 16: ...V Register 956 26 Enhanced Universal Serial Communication Interface eUSCI I2 C Mode 957 26 1 Enhanced Universal Serial Communication Interface B eUSCI_B Overview 958 26 2 eUSCI_B Introduction I2 C Mod...

Page 17: ...on 997 27 2 1 Power Management 997 27 2 2 Clock System 997 27 2 3 Interrupts 997 27 2 4 Memory 998 27 2 5 LCD_F Functional Operation 999 27 3 LCD_F Registers 1015 27 3 1 LCDCTL Register 1021 27 3 2 LC...

Page 18: ...2 11 RNR Register 102 2 12 RBAR Register 103 2 13 RASR Register 104 2 14 RBAR_A1 Register 106 2 15 RASR_A1 Register 107 2 16 RBAR_A2 Register 109 2 17 RASR_A2 Register 110 2 18 RBAR_A3 Register 112 2...

Page 19: ...Register 146 2 60 SHCSR Register 147 2 61 CFSR Register 149 2 62 HFSR Register 151 2 63 DFSR Register 152 2 64 MMFAR Register 153 2 65 BFAR Register 154 2 66 AFSR Register 155 2 67 PFR0 Register 156...

Page 20: ...ister 205 2 109 MASK1 Register 206 2 110 FUNCTION1 Register 207 2 111 COMP2 Register 209 2 112 MASK2 Register 210 2 113 FUNCTION2 Register 211 2 114 COMP3 Register 213 2 115 MASK3 Register 214 2 116 F...

Page 21: ...gister 265 3 9 RSTCTL_PSSRESET_STAT Register 266 3 10 RSTCTL_PSSRESET_CLR Register 266 3 11 RSTCTL_PCMRESET_STAT Register 267 3 12 RSTCTL_PCMRESET_CLR Register 267 3 13 RSTCTL_PINRESET_STAT Register 2...

Page 22: ...ies for MSP432P401xx MCU 337 5 10 SYS_REBOOT_CTL Register 339 5 11 SYS_NMI_CTLSTAT Register 340 5 12 SYS_WDTRESET_CTL Register 341 5 13 SYS_PERIHALT_CTL Register 342 5 14 SYS_SRAM_SIZE Register 343 5...

Page 23: ...Power Mode Transitions 431 8 3 Valid Active Mode Transitions 432 8 4 Valid LPM0 Transitions 432 8 5 Valid LPM3 and LPM4 Transitions 433 8 6 Valid LPM3 5 and LPM4 5 Transitions 434 8 7 Active Mode Tran...

Page 24: ...PROT Register 501 9 37 FLCTL_BANK0_MAIN_WEPROT Register 502 9 38 FLCTL_BANK1_INFO_WEPROT Register 504 9 39 FLCTL_BANK1_MAIN_WEPROT Register 505 9 40 FLCTL_BMRK_CTLSTAT Register 507 9 41 FLCTL_BMRK_IFE...

Page 25: ...3 Register 563 10 30 FLCTL_PRGBRST_DATA3_0 Register 564 10 31 FLCTL_PRGBRST_DATA3_1 Register 564 10 32 FLCTL_PRGBRST_DATA3_2 Register 565 10 33 FLCTL_PRGBRST_DATA3_3 Register 565 10 34 FLCTL_ERASE_CTL...

Page 26: ...ple 632 11 6 Memory Scatter Gather Example 635 11 7 Peripheral Scatter Gather Example 638 11 8 Memory Map for 32 Channels Including the Alternate Data Structure 640 11 9 Memory Map for Three DMA Chann...

Page 27: ...2 Capacitive Touch IO Block Diagram 711 14 3 CAPTIOxCTL Register 713 15 1 LFSR Implementation of CRC CCITT as Defined in Standard Bit0 is MSB 715 15 2 LFSR Implementation of CRC32 ISO3309 as Defined i...

Page 28: ...ONTROL2 Register 777 18 12 T32INTCLR2 Register 778 18 13 T32RIS2 Register 779 18 14 T32MIS2 Register 780 18 15 T32BGLOAD2 Register 781 19 1 Timer_A Block Diagram 784 19 2 Up Mode 786 19 3 Up Mode Flag...

Page 29: ...Register 829 20 28 RTCADAY Register 829 20 29 RTCPS0CTL Register 830 20 30 RTCPS1CTL Register 831 20 31 RTCPS0 Register 832 20 32 RTCPS1 Register 832 20 33 RTCIV Register 833 20 34 RTCBIN2BCD Registe...

Page 30: ...3 23 8 CExCTL0 Register 896 23 9 CExCTL1 Register 897 23 10 CExCTL2 Register 898 23 11 CExCTL3 Register 899 23 12 CExINT Register 901 23 13 CExIV Register 902 24 1 eUSCI_Ax Block Diagram UART Mode UCS...

Page 31: ...us 961 26 5 I2 C Module 7 Bit Addressing Format 961 26 6 I2 C Module 10 Bit Addressing Format 962 26 7 I2 C Module Addressing Format With Repeated START Condition 962 26 8 I2 C Time Line Legend 962 26...

Page 32: ...xample 2 Mux Waveforms 1008 27 9 Example 3 Mux Waveforms 1009 27 10 Example 4 Mux Waveforms 1010 27 11 Example 6 Mux Waveforms 1011 27 12 Example 8 Mux 1 3 Bias Waveforms LCDLP 0 1012 27 13 Example 8...

Page 33: ...scriptions 94 2 9 FPCAR Register Field Descriptions 95 2 10 FPDSCR Register Field Descriptions 96 2 11 MVFR0 Register Field Descriptions 97 2 12 MVFR1 Register Field Descriptions 98 2 13 MPU Registers...

Page 34: ...ster Field Descriptions 133 2 57 STCR Register Field Descriptions 134 2 58 SCB Registers 135 2 59 CPUID Register Field Descriptions 136 2 60 ICSR Register Field Descriptions 137 2 61 VTOR Register Fie...

Page 35: ...188 2 106 FP_COMP6 Register Field Descriptions 189 2 107 FP_COMP7 Register Field Descriptions 190 2 108 DWT Registers 191 2 109 CTRL Register Field Descriptions 192 2 110 CYCCNT Register Field Descrip...

Page 36: ...2 155 STIM25 Register Field Descriptions 243 2 156 STIM26 Register Field Descriptions 244 2 157 STIM27 Register Field Descriptions 245 2 158 STIM28 Register Field Descriptions 246 2 159 STIM29 Regist...

Page 37: ...Description 301 4 18 SYS_SRAM_BANKRET Register Description 302 4 19 SYS_FLASH_SIZE Register Description 303 4 20 SYS_DIO_GLTFLT_CTL Register Description 304 4 21 SYS_SECDATA_UNLOCK Register Descriptio...

Page 38: ..._BOOTOVER_ACK Register Description 374 5 37 SYS_RESET_REQ Register Description 375 5 38 SYS_RESET_STATOVER Register Description 376 5 39 SYS_SYSTEM_STAT Register Description 377 6 1 HFXTFREQ Settings...

Page 39: ...p Auto Verify Before Program Operations 462 9 10 MSP432 Driver Library API for Enabling Program Operations 463 9 11 MSP432 Driver Library API for Flash Erase Operations 471 9 12 FLCTL Registers 475 9...

Page 40: ...tion 522 10 1 MSP432 Driver Library API for FLCTL_A Wait State Configuration 525 10 2 MSP432 Driver Library API for FLCTL_A Read Buffering Configuration 526 10 3 MSP432 Driver Library API for FLCTL_A...

Page 41: ...574 10 47 FLCTL_BMRK_IFETCH Register Description 575 10 48 FLCTL_BMRK_DREAD Register Description 576 10 49 FLCTL_BMRK_CMP Register Description 577 10 50 FLCTL_IFG Register Description 578 10 51 FLCTL_...

Page 42: ...FG Register Description 653 11 19 DMA_INT2_SRCCFG Register Description 654 11 20 DMA_INT3_SRCCFG Register Description 655 11 21 DMA_INT0_SRCFLG Register Description 656 11 22 DMA_INT0_CLRFLG Register...

Page 43: ...xCTL Register Description 713 15 1 CRC32 Registers 717 15 2 CRC32DI Register Description 718 15 3 CRC32DIRB Register Description 719 15 4 CRC32INIRES_LO Register Description 720 15 5 CRC32INIRES_HI Re...

Page 44: ...r Description 780 18 15 T32BGLOAD2 Register Description 781 19 1 Timer Modes 786 19 2 Output Modes 791 19 3 Timer_A Registers 796 19 4 TAxCTL Register Description 797 19 5 TAxR Register Description 79...

Page 45: ...ster Description 860 22 6 ADC14CTL1 Register Description 863 22 7 ADC14LO0 Register Description 865 22 8 ADC14HI0 Register Description 866 22 9 ADC14LO1 Register Description 867 22 10 ADC14HI1 Registe...

Page 46: ...ter Description 948 25 9 UCAxIFG Register Description 949 25 10 UCAxIV Register Description 950 25 11 eUSCI_B SPI Registers 951 25 12 UCBxCTLW0 Register Description 952 25 13 UCBxBRW Register Descript...

Page 47: ...ng Memory Registers 1018 27 7 LCD_F Animation Memory Registers 1020 27 8 LCDCTL Register Description 1021 27 9 LCDBMCTL Register Description 1023 27 10 LCDVCTL Register Description 1025 27 11 LCDPCTL0...

Page 48: ...reads as 0 0 1 Condition after Soft Reset or higher class reset 0 1 Condition after Hard Reset or higher class reset 0 1 Condition after Reboot Reset or higher class reset 0 1 Condition after POR See...

Page 49: ...des a high performance low cost platform that meets the system requirements of minimal memory implementation reduced pin count and low power consumption while delivering outstanding computational perf...

Page 50: ...instruction and hardware divide Atomic bit manipulation bit banding delivering maximum memory utilization and streamlined peripheral control Unaligned data access enabling data to be efficiently pack...

Page 51: ...ven while SYSRESETn is asserted Support for Serial Wire and JTAG based debug ports Flash Patch and Breakpoint FPB unit for implementing hardware breakpoints Data Watchpoint and Trace DWT unit for impl...

Page 52: ...etic and dedicated hardware division To facilitate the design of cost sensitive devices the Cortex M4F processor implements tightly coupled system components that reduce processor area while significa...

Page 53: ...Instruction ICODE and Data DCODE accesses during code execution Table 1 2 lists the slaves mapped on each of these buses NOTE The exact address range for each of the bus interfaces can be found in the...

Page 54: ...d an off chip Trace analyzer For more information on each of these blocks see Section 2 3 in Cortex M4 Peripherals 1 2 3 Cortex M4F System Component Details The Cortex M4F includes the following syste...

Page 55: ...cess to all resources In Thread mode the CONTROL register controls whether software execution is privileged or unprivileged In Handler mode software execution is always privileged Only privileged soft...

Page 56: ...name so the base address is n a not applicable and there is no offset Figure 1 2 Cortex M4F Register Set 1 3 4 Register Descriptions This section lists and describes the Cortex M4F registers The core...

Page 57: ...privileged mode the PSP can be accessed in either privileged or unprivileged mode 1 3 4 3 Register 14 Link Register LR R14 The Link Register LR is register R14 and it stores the return information for...

Page 58: ...R and IPSR IEPSR RO EPSR and IPSR IAPSR RW 1 APSR and IPSR EAPSR RW 2 APSR and EPSR 1 3 4 6 Register 17 Priority Mask Register PRIMASK The PRIMASK register prevents activation of all exceptions with p...

Page 59: ...rtex M4 instruction set chapter in the Cortex M4 Devices Generic User Guide 1 3 4 10 Register 21 Floating Point Status Control FPSC The FPSC register provides all necessary user level control of the f...

Page 60: ...nts Incorporated Cortex M4F Processor 1 4 1 Memory Regions Types and Attributes The memory map and the programming of the MPU split the memory map into regions Each region has a defined memory type an...

Page 61: ...e or Strongly Ordered memory and if A1 occurs before A2 in program order A1 is always observed before A2 1 4 3 Behavior of Memory Accesses Table 1 5 shows the behavior of accesses to each region in th...

Page 62: ...the operations The DMB instruction ensures that if the exception is taken immediately after being enabled the processor uses the new exception vector Self modifying code If a program contains self mo...

Page 63: ...d to bit band region A write operation is performed as read modify write Instruction accesses are not permitted The following formula shows how the alias region maps onto the bit band region bit_word_...

Page 64: ...the bit band region Writing a value with bit 0 set writes a 1 to the bit band bit and writing a value with bit 0 clear writes a 0 to the bit band bit Bits 31 1 of the alias word have no effect on the...

Page 65: ...ity 0 is treated as fourth priority after a Reset Non Maskable Interrupt NMI and a Hard Fault in that order 0 is the default priority for all the programmable priorities NOTE Vector table entries are...

Page 66: ...use an exception cannot be managed by any other exception mechanism Hard faults have a fixed priority of 1 meaning they have higher priority than any exception with configurable priority Memory Manage...

Page 67: ...n 1 5 4 3 See SHPR1 register 4 See IPRn registers Table 1 8 Exception Types Exception Type Vector Number Priority 1 Vector Address or Offset 2 Activation 0 0x0000_0000 Stack top is loaded from the fir...

Page 68: ...he vector table contains the reset value of the stack pointer and the start addresses also called exception vectors for all exception handlers The vector table is constructed using the vector address...

Page 69: ...y control in systems with interrupts the NVIC supports priority grouping This grouping divides each interrupt priority register entry into two fields An upper field that defines the group priority A l...

Page 70: ...xception handler was not handling a late arriving exception The processor pops the stack and restores the processor state to the state it had before the interrupt occurred See Section 1 5 8 2 for more...

Page 71: ...eturn address which is the address of the next instruction in the interrupted program This value is restored to the PC at exception return so that the interrupted program resumes In parallel with the...

Page 72: ...ion return uses floating point state from MSP Execution uses MSP after return 0xFFFF_FFE2 0xFFFF_FFE8 Reserved 0xFFFF_FFE9 Return to Thread mode Exception return uses floating point state from MSP Exe...

Page 73: ...servation Bus fault Bus Fault Status Register BFSR BLSPERR Precise data bus error Bus fault Bus Fault Status Register BFSR PRECISERR Imprecise data bus error Bus fault Bus Fault Status Register BFSR I...

Page 74: ...SR Configurable Fault Status Register CFSR Usage fault Usage Fault Status Register UFSR Configurable Fault Status Register CFSR NOTE MMFSR BFSR and UFSR together form the Configurable Fault Status CFS...

Page 75: ...e Address AND ANDS Rd Rn Op2 Logical AND N Z C ASR ASRS Rd Rm Rs n Arithmetic Shift Right N Z C B label Branch BFC Rd lsb width Bit Field Clear BFI Rd Rn lsb width Bit Field Insert BIC BICS Rd Rn Op2...

Page 76: ...bit result N Z MVN MVNS Rd Op2 Move NOT N Z C NOP No Operation ORN ORNS Rd Rn Op2 Logical OR NOT N Z C ORR ORRS Rd Rn Op2 Logical OR N Z C PKHTB PKHBT Rd Rn Rm Op2 Pack Halfword POP reglist Pop regis...

Page 77: ...umulate SMMLS SMMLR Rd Rn Rm Ra Signed Most significant word Multiply Subtract SMMUL SMMULR Rd Rn Rm Signed Most significant word Multiply SMUAD Rd Rn Rm Signed dual Multiply Add Q SMULBB SMULBT SMULT...

Page 78: ...ult UMULL RdLo RdHi Rn Rm Unsigned Multiply 32 x 32 64 bit result UQADD16 Rd Rn Rm Unsigned Saturating Add 16 UQADD8 Rd Rn Rm Unsigned Saturating Add 8 UQASX Rd Rn Rm Unsigned Saturating Add and Subtr...

Page 79: ...2 64 Dd Sd Rn Load an extension register from memory VLMA F32 Sd Sn Sm Floating point Multiply Accumulate VLMS F32 Sd Sn Sm Floating point Multiply Subtract VMOV F32 Sd imm Floating point Move immedia...

Page 80: ...5 Revised June 2019 Cortex M4F Peripherals This chapter provides information on the implementation of the Arm Cortex M4F processor peripherals in MSP432P4xx devices Topic Page 2 1 Cortex M4F Periphera...

Page 81: ...address map of the Private Peripheral Bus PPB Some peripheral register regions are split into two address regions as indicated by two addresses listed Table 2 1 Core Peripheral Register Regions Addre...

Page 82: ...e undefined at reset the correct initialization sequence for the SysTick counter is 1 Program the value in the STRVR register 2 Clear the STCVR register by writing to it with any value 3 Configure the...

Page 83: ...esponding interrupt set pending register bit or to the Software Trigger Interrupt Register STIR to make a Software Generated Interrupt pending See the INT bit in the IPSR0 register or the STIR registe...

Page 84: ...e processor Each memory region of size above 256 bytes can be divided into 8 sub regions of equal size and each of these sub regions can be selectively disabled for protection via MPU When memory regi...

Page 85: ...le 000b 0 1 0 Normal Not shareable Outer and inner write through No write allocate 000b 1 1 0 Normal Shareable 000b 0 1 1 Normal Not shareable 000b 1 1 1 Normal Shareable 001b 0 0 0 Normal Not shareab...

Page 86: ...e back write allocate Peripherals 000b 1 0 1 Device memory shareable In current MSP432P4xx family microcontroller implementations the shareability and cache policy attributes do not affect the system...

Page 87: ...gion Using Multi Word Writes The MPU can be programmed directly using multi word writes depending how the information is divided Consider the following reprogramming R1 region number R2 address R3 siz...

Page 88: ...rocessing operations Combined multiply and accumulate instructions for increased precision Fused MAC Hardware support for conversion addition subtraction multiplication with optional accumulate divisi...

Page 89: ...VNEG and VMOV are not considered arithmetic CDP operations and are not affected by Flush to Zero mode A result that is tiny as described in the IEEE 754 standard where the destination precision is sm...

Page 90: ...gardless of the fractions of any NaN operands SNaNs in an arithmetic CDP operation set the IOC flag FPSCR 0 NaN handling by data transfer and non arithmetic CDP instructions is the same as in full com...

Page 91: ...re information 2 2 5 7 Enabling the FPU The FPU is disabled from reset You must enable it before you can use any floating point instructions In many compilers such as in TI s Code Composer Studio IDE...

Page 92: ...rates the order in which packets are output The different sources in decreasing order of priority are Software trace Software can write directly to ITM stimulus registers to generate packets Hardware...

Page 93: ...rtex M4 Peripheral SysTick NVIC MPU FPU and SCB registers The offset listed is a hexadecimal increment to the register s address relative to the Core Peripherals base address of 0xE000_E000 NOTE Regis...

Page 94: ...ate automatically being preserved on exception entry 30 LSPEN R W 1h Lazy State Preservation Enable When the processor performs a context save space on the stack is reserved for the floating point sta...

Page 95: ...f the unpopulated floating point register space allocated on an exception stack frame The FPCAR points to the stack location reserved for S0 Figure 2 5 FPCAR Register 31 30 29 28 27 26 25 24 RESERVED...

Page 96: ...0h R W 0h R W 0h R W 0h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED R W 0h Table 2 10 FPDSCR Register Field Descriptions Bit Field Type Reset Description 31 27 RESERVED R W 0h 26 AHP R W 0h Default...

Page 97: ...hardware The value of this field is 0b0001 all rounding modes supported 27 24 SHORT_VECTORS R 0h Indicates the hardware support for FP short vectors The value of this field is 0b0000 not supported in...

Page 98: ...0h R 1h R 1h Table 2 12 MVFR1 Register Field Descriptions Bit Field Type Reset Description 31 28 FP_FUSED_MAC R 1h Indicates whether the FP supports fused multiply accumulate operations The value of...

Page 99: ...4 2 2 D98h RNR MPU Region Number Register read write 00000000h Section 2 4 2 3 D9Ch RBAR MPU Region Base Address Register read write 00000000h Section 2 4 2 4 DA0h RASR MPU Region Attribute and Size...

Page 100: ...TYPE Register 31 30 29 28 27 26 25 24 RESERVED R 0h 23 22 21 20 19 18 17 16 IREGION R 0h 15 14 13 12 11 10 9 8 DREGION R 8h 7 6 5 4 3 2 1 0 RESERVED SEPARATE R 0h R 0h Table 2 14 TYPE Register Field D...

Page 101: ...19 18 17 16 RESERVED R W 0h 15 14 13 12 11 10 9 8 RESERVED R W 0h 7 6 5 4 3 2 1 0 RESERVED PRIVDEFENA HFNMIENA ENABLE R W 0h R W 0h R W 0h R W 0h Table 2 15 CTRL Register Field Descriptions Bit Field...

Page 102: ...U Region Base Address Register or the MPU Attributes and Size Register to configure the characteristics of the protection region Figure 2 11 RNR Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 1...

Page 103: ...LID always reads back as 0 Writing with VALID 1 and REGION n changes the region number to n This is a short hand way to write the MPU Region Number Register This register is Unpredictable if accessed...

Page 104: ...W 0h R W 0h 23 22 21 20 19 18 17 16 RESERVED TEX S C B R W 0h R W 0h R W 0h R W 0h R W 0h 15 14 13 12 11 10 9 8 SRD R W 0h 7 6 5 4 3 2 1 0 RESERVED SIZE ENABLE R W 0h R W 0h R W 0h Table 2 18 RASR Re...

Page 105: ...corresponding sub region Regions are split into eight equal sized sub regions Sub regions are not supported for region sizes of 128 bytes and less 7 6 RESERVED R W 0h 5 1 SIZE R W 0h MPU Protection Re...

Page 106: ...ADDR R W 0h 7 6 5 4 3 2 1 0 ADDR VALID REGION R W 0h R W 0h R W 0h Table 2 19 RBAR_A1 Register Field Descriptions Bit Field Type Reset Description 31 5 ADDR R W 0h Region base address field The positi...

Page 107: ...d Type Reset Description 31 29 RESERVED R W 0h 28 XN R W 0h Instruction access disable bit 0b enable instruction fetches 1b disable instruction fetches 27 RESERVED R W 0h 26 24 AP R W 0h Data access p...

Page 108: ...ions are split into eight equal sized sub regions Sub regions are not supported for region sizes of 128 bytes and less 7 6 RESERVED R W 0h 5 1 SIZE R W 0h MPU Protection Region Size Field 0b Reserved...

Page 109: ...ADDR R W 0h 7 6 5 4 3 2 1 0 ADDR VALID REGION R W 0h R W 0h R W 0h Table 2 21 RBAR_A2 Register Field Descriptions Bit Field Type Reset Description 31 5 ADDR R W 0h Region base address field The positi...

Page 110: ...d Type Reset Description 31 29 RESERVED R W 0h 28 XN R W 0h Instruction access disable bit 0b enable instruction fetches 1b disable instruction fetches 27 RESERVED R W 0h 26 24 AP R W 0h Data access p...

Page 111: ...ions are split into eight equal sized sub regions Sub regions are not supported for region sizes of 128 bytes and less 7 6 RESERVED R W 0h 5 1 SIZE R W 0h MPU Protection Region Size Field 0b Reserved...

Page 112: ...ADDR R W 0h 7 6 5 4 3 2 1 0 ADDR VALID REGION R W 0h R W 0h R W 0h Table 2 23 RBAR_A3 Register Field Descriptions Bit Field Type Reset Description 31 5 ADDR R W 0h Region base address field The positi...

Page 113: ...d Type Reset Description 31 29 RESERVED R W 0h 28 XN R W 0h Instruction access disable bit 0b enable instruction fetches 1b disable instruction fetches 27 RESERVED R W 0h 26 24 AP R W 0h Data access p...

Page 114: ...ions are split into eight equal sized sub regions Sub regions are not supported for region sizes of 128 bytes and less 7 6 RESERVED R W 0h 5 1 SIZE R W 0h MPU Protection Region Size Field 0b Reserved...

Page 115: ...4h IABR1 Irq 32 to 63 Active Bit Register read only 00000000h Section 2 4 3 10 400h IPR0 Irq 0 to 3 Priority Register read write 00000000h Section 2 4 3 11 404h IPR1 Irq 4 to 7 Priority Register read...

Page 116: ...31 0 SETENA R W 0h Writing 0 to a SETENA bit has no effect writing 1 to a bit enables the corresponding interrupt Reading the bit returns its current enable state Reset clears the SETENA fields 2 4 3...

Page 117: ...31 0 CLRENA R W 0h Writing 0 to a CLRENA bit has no effect writing 1 to a bit disables the corresponding interrupt Reading the bit returns its current enable state Reset clears the CLRENA field 2 4 3...

Page 118: ...tions Bit Field Type Reset Description 31 0 SETPEND R W 0h Writing 0 to a SETPEND bit has no effect writing 1 to a bit pends the corresponding interrupt Reading the bit returns its current state 2 4 3...

Page 119: ...Field Type Reset Description 31 0 CLRPEND R W 0h Writing 0 to a CLRPEND bit has no effect writing 1 to a bit clears the corresponding pending interrupt Reading the bit returns its current state 2 4 3...

Page 120: ...Field Type Reset Description 31 0 ACTIVE R 0h Interrupt active flags Reading 0 implies the interrupt is not active or stacked Reading 1 implies the interrupt is active or pre empted and stacked 2 4 3...

Page 121: ...ERVED R 0h 23 21 PRI_2 R W 0h Priority of interrupt 2 16 20 RESERVED R 0h 15 13 PRI_1 R W 0h Priority of interrupt 1 8 12 RESERVED R 0h 7 5 PRI_0 R W 0h Priority of interrupt 0 0 4 RESERVED R 0h 2 4 3...

Page 122: ...R 0h 23 21 PRI_10 R W 0h Priority of interrupt 10 16 20 RESERVED R 0h 15 13 PRI_9 R W 0h Priority of interrupt 9 8 12 RESERVED R 0h 7 5 PRI_8 R W 0h Priority of interrupt 8 0 4 RESERVED R 0h 2 4 3 14...

Page 123: ...R 0h 23 21 PRI_18 R W 0h Priority of interrupt 18 16 20 RESERVED R 0h 15 13 PRI_17 R W 0h Priority of interrupt 17 8 12 RESERVED R 0h 7 5 PRI_16 R W 0h Priority of interrupt 16 0 4 RESERVED R 0h 2 4 3...

Page 124: ...R 0h 23 21 PRI_26 R W 0h Priority of interrupt 26 16 20 RESERVED R 0h 15 13 PRI_25 R W 0h Priority of interrupt 25 8 12 RESERVED R 0h 7 5 PRI_24 R W 0h Priority of interrupt 24 0 4 RESERVED R 0h 2 4 3...

Page 125: ...R 0h 23 21 PRI_34 R W 0h Priority of interrupt 34 16 20 RESERVED R 0h 15 13 PRI_33 R W 0h Priority of interrupt 33 8 12 RESERVED R 0h 7 5 PRI_32 R W 0h Priority of interrupt 32 0 4 RESERVED R 0h 2 4 3...

Page 126: ...R 0h 23 21 PRI_42 R W 0h Priority of interrupt 42 16 20 RESERVED R 0h 15 13 PRI_41 R W 0h Priority of interrupt 41 8 12 RESERVED R 0h 7 5 PRI_40 R W 0h Priority of interrupt 40 0 4 RESERVED R 0h 2 4 3...

Page 127: ...R 0h 23 21 PRI_50 R W 0h Priority of interrupt 50 16 20 RESERVED R 0h 15 13 PRI_49 R W 0h Priority of interrupt 49 8 12 RESERVED R 0h 7 5 PRI_48 R W 0h Priority of interrupt 48 0 4 RESERVED R 0h 2 4 3...

Page 128: ...R 0h 23 21 PRI_58 R W 0h Priority of interrupt 58 16 20 RESERVED R 0h 15 13 PRI_57 R W 0h Priority of interrupt 57 8 12 RESERVED R 0h 7 5 PRI_56 R W 0h Priority of interrupt 56 0 4 RESERVED R 0h 2 4 3...

Page 129: ...errupt Register Use the Software Trigger Interrupt Register to pend an interrupt to trigger Figure 2 46 STIR Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2...

Page 130: ...listed in Table 2 53 should be considered as reserved locations and the register contents should not be modified Table 2 53 SYSTICK Registers Offset Acronym Register Name Type Reset Section 10h STCSR...

Page 131: ...13 12 11 10 9 8 RESERVED R W 0h 7 6 5 4 3 2 1 0 RESERVED CLKSOURCE TICKINT ENABLE R W 0h R 1h R W 0h R W 0h Table 2 54 STCSR Register Field Descriptions Bit Field Type Reset Description 31 17 RESERVE...

Page 132: ...nto the current value register when the counter reaches 0 It can be any value between 1 and 0x00FFFFFF A start value of 0 is possible but has no effect because the SysTick interrupt and COUNTFLAG are...

Page 133: ...urrent value in the register Figure 2 49 STCVR Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED CURRENT R W R W Table 2 56 STCVR Register Field D...

Page 134: ...vide and multiply Figure 2 50 STCR Register 31 30 29 28 27 26 25 24 NOREF SKEW RESERVED R R R 23 22 21 20 19 18 17 16 TENMS R 15 14 13 12 11 10 9 8 TENMS R 7 6 5 4 3 2 1 0 TENMS R Table 2 57 STCR Regi...

Page 135: ...Configurable Fault Status Registers read write 00000000h Section 2 4 5 11 D2Ch HFSR Hard Fault Status Register read write 00000000h Section 2 4 5 12 D30h DFSR Debug Fault Status Register read write 0...

Page 136: ...e the version number of the processor core the implementation details of the processor core Figure 2 51 CPUID Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 IMPLEMENTER VARIANT CONSTANT R 41...

Page 137: ...escriptions Bit Field Type Reset Description 31 NMIPENDSET R W 0h Set pending NMI bit NMIPENDSET pends and activates an NMI Because NMI is the highest priority interrupt it takes effect as soon as it...

Page 138: ...r Field Descriptions continued Bit Field Type Reset Description 17 12 VECTPENDING R 0h Pending ISR number field VECTPENDING contains the interrupt number of the highest priority pending ISR 11 RETTOBA...

Page 139: ...he vector table is in RAM or code memory the vector table offset Figure 2 53 VTOR Register 31 30 29 28 27 26 25 24 RESERVED TBLBASE TBLOFF R W 0h R W 0h R W 0h 23 22 21 20 19 18 17 16 TBLOFF R W 0h 15...

Page 140: ...t change ENDIANNESS outside of reset 0b R W little endian 1b R W big endian 14 11 RESERVED R W 0h 10 8 PRIGROUP R W 0h Interrupt priority grouping field The PRIGROUP field is a binary point position i...

Page 141: ...struments Incorporated Cortex M4F Peripherals Table 2 62 AIRCR Register Field Descriptions continued Bit Field Type Reset Description 0 VECTRESET W 0h System Reset bit Resets the system with the excep...

Page 142: ...R W 0h R W 0h R W 0h R W 0h R W 0h Table 2 63 SCR Register Field Descriptions Bit Field Type Reset Description 31 5 RESERVED R W 0h 4 SEVONPEND R W 0h When enabled this causes WFE to wake up when an...

Page 143: ...e it is saved The SP is restored on the associated exception return 8 BFHFNMIGN R W 0h When enabled this causes handlers running at priority 1 and 2 Hard Fault NMI and FAULTMASK escalated handlers to...

Page 144: ...r SVC SysTick PendSV System Handlers are a special class of exception handler that can have their priority set to any of the priority levels Most can be masked on enabled or off disabled When disabled...

Page 145: ...SVC SysTick PendSV System Handlers are a special class of exception handler that can have their priority set to any of the priority levels Most can be masked on enabled or off disabled When disabled t...

Page 146: ...SysTick PendSV System Handlers are a special class of exception handler that can have their priority set to any of the priority levels Most can be masked on enabled or off disabled When disabled the...

Page 147: ...14 13 12 11 10 9 8 SVCALLPEND ED BUSFAULTPE NDED MEMFAULTPE NDED USGFAULTPE NDED SYSTICKACT PENDSVACT RESERVED MONITORACT R 0h R 0h R 0h R 0h R 0h R 0h R W 0h R 0h 7 6 5 4 3 2 1 0 SVCALLACT RESERVED...

Page 148: ...ENDSVACT R 0h PendSV active flag 0b R W not active 1b R W active 9 RESERVED R W 0h 8 MONITORACT R 0h the Monitor active flag 0b R W not active 1b R W active 7 SVCALLACT R 0h SVCall active flag 0b R W...

Page 149: ...Register is enabled and an SDIV or UDIV instruction is used with a divisor of 0 this fault occurs The instruction is executed and the return PC points to it If DIV_0_TRP is not set then the divide re...

Page 150: ...or The fault stops on the instruction so if the error occurs under a branch shadow no fault occurs The BFAR is not written 7 MMARVALID R W 0h Memory Manage Address Register MMAR address valid flag A l...

Page 151: ...ble 2 70 HFSR Register Field Descriptions Bit Field Type Reset Description 31 DEBUGEVT R W 0h This bit is set if there is a fault related to debug This is only possible when halting debug is not enabl...

Page 152: ...status register and some are ignored Figure 2 63 DFSR Register 31 30 29 28 27 26 25 24 RESERVED R W 0h 23 22 21 20 19 18 17 16 RESERVED R W 0h 15 14 13 12 11 10 9 8 RESERVED R W 0h 7 6 5 4 3 2 1 0 RES...

Page 153: ...age Fault Figure 2 64 MMFAR Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ADDRESS R W Table 2 72 MMFAR Register Field Descriptions Bit Field Type Reset...

Page 154: ...of the location that generated a Bus Fault Figure 2 65 BFAR Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ADDRESS R W Table 2 73 BFAR Register Field D...

Page 155: ...o the AUXFAULT inputs of the processor and a single cycle high level on an external pin causes the corresponding AFSR bit to become latched as one The bit can only be cleared by writing a one to the c...

Page 156: ...16 RESERVED R 0h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED STATE1 STATE0 R 0h R 3h R 0h Table 2 75 PFR0 Register Field Descriptions Bit Field Type Reset Description 31 8 RESERVED R 0h 7 4 STATE1...

Page 157: ...cessor Feature register1 Processor Feature register1 Figure 2 68 PFR1 Register 31 30 29 28 27 26 25 24 RESERVED R 0h 23 22 21 20 19 18 17 16 RESERVED R 0h 15 14 13 12 11 10 9 8 RESERVED MICROCONTROLLE...

Page 158: ...of the debug system Further details are provided in the debug infrastructure itself Figure 2 69 DFR0 Register 31 30 29 28 27 26 25 24 RESERVED R 0h 23 22 21 20 19 18 17 16 MICROCONTROLLER_DEBUG_MODEL...

Page 159: ...0 Register Offset D4Ch reset 00000000h AFR0 is shown in Figure 2 70 and described in Table 2 78 Auxiliary Feature register0 RESERVED Figure 2 70 AFR0 Register 31 30 29 28 27 26 25 24 RESERVED R 0 23 2...

Page 160: ...Bit Field Type Reset Description 31 24 RESERVED R 0h 23 20 AUILIARY_REGISTER_S UPPORT R 1h Auxiliary register support 0b R W not supported 1b R W Auxiliary control register 19 16 RESERVED R 0h 15 12...

Page 161: ...0000h MMFR1 is shown in Figure 2 72 and described in Table 2 80 Memory Model Feature register1 General information on the memory model and memory management support Figure 2 72 MMFR1 Register 31 30 29...

Page 162: ...egister2 General information on the memory model and memory management support Figure 2 73 MMFR2 Register 31 30 29 28 27 26 25 24 RESERVED WAIT_FOR_INTERRUPT_STALLING R 0h R 1h 23 22 21 20 19 18 17 16...

Page 163: ...0000h MMFR3 is shown in Figure 2 74 and described in Table 2 82 Memory Model Feature register3 General information on the memory model and memory management support Figure 2 74 MMFR3 Register 31 30 29...

Page 164: ...28 RESERVED R 0h 27 24 DIVIDE_INSTRS R 1h Divide instructions 0b R W no divide instructions present 1b R W adds SDIV UDIV v1 quotient only result 23 20 DEBUG_INSTRS R 1h Debug instructions 0b R W no...

Page 165: ...1 Register Field Descriptions Bit Field Type Reset Description 31 28 RESERVED R 0h 27 24 INTERWORK_INSTRS R 2h Interwork instructions 0b R W no interworking instructions supported 1b R W adds BX and T...

Page 166: ...ns present 1b R W adds REV REV16 REVSH 10b R W adds RBIT 27 24 RESERVED R 1h 23 20 MULTU_INSTRS R 2h Multiply instructions advanced unsigned 0b R W no unsigned multiply instructions present 1b R W add...

Page 167: ...egister dependencies 1b R W adds true NOP and the capability of additional NOP compatible hints 23 20 THUMBCOPY_INSTRS R 1h ThumbCopy instructions 0b R W Thumb MOV register instruction does not allow...

Page 168: ...pport 11b R W adds CLREX LDREXB STREXB LDREXH STREXH 19 16 BARRIER_INSTRS R 1h Barrier instructions 0b R W no barrier instructions supported 1b R W adds DMB DSB ISB barrier instructions 15 12 RESERVED...

Page 169: ...ter Field Descriptions Bit Field Type Reset Description 31 24 RESERVED R W 0h 23 22 CP11 R W 3h Access privileges for coprocessor 11 The possible values of each field are 00b Access denied Any attempt...

Page 170: ...9 lists the memory mapped registers for the SCnSCB All register offset addresses not listed in Table 2 89 should be considered as reserved locations and the register contents should not be modified Ta...

Page 171: ...rrupt Controller Type Register to see the number of interrupt lines that the NVIC supports Figure 2 81 ICTR Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RESERVED R 0h 15 14 13 12 11 10 9 8...

Page 172: ...F DISMCYCINT R W 0h R W 0h R W 0h R W 0h Table 2 91 ACTLR Register Field Descriptions Bit Field Type Reset Description 31 10 RESERVED R W 0h Reserved 9 DISOOFP R W 0h Disables floating point instructi...

Page 173: ...2 92 should be considered as reserved locations and the register contents should not be modified Table 2 92 COREDEBUG Registers Offset Acronym Register Name Type Reset Section DF0h DHCSR Debug Haltin...

Page 174: ...bit Bit 16 of DHCSR is Unpredictable on reset Figure 2 83 DHCSR Register 31 30 29 28 27 26 25 24 RESERVED S_RESET_ST S_RETIRE_ST rw 0 r 0 r 0 23 22 21 20 19 18 17 16 RESERVED S_LOCKUP S_SLEEP S_HALT...

Page 175: ...nly be modified when the processor is halted S_HALT 1 Also does not affect fault exceptions and SVC caused by execution of the instructions CMASKINTS must be set or cleared before halt is released Thi...

Page 176: ...s some read as 0 when using MRS instructions Note that all bits can be written but some combinations cause a fault when execution is resumed Note that IT might be written and behaves as though in an I...

Page 177: ...ves a request from the Debug Core Register Selector this register is read or written by the processor using a normal load store unit operation If core register transfers are not being performed softwa...

Page 178: ...val optimization must suppress it in this case Figure 2 86 DEMCR Register 31 30 29 28 27 26 25 24 RESERVED TRCENA rw 0 rw 0 23 22 21 20 19 18 17 16 RESERVED MON_REQ MON_STEP MON_PEND MON_EN rw 0 rw 0...

Page 179: ...a vector catch has triggered 1 If a fault is taken during vectoring vector read or stack push error the halt occurs on the corresponding fault handler for the vector error or stack push 2 If a late ar...

Page 180: ...the register contents should not be modified Table 2 97 FPB Registers Offset Acronym Register Name Type Reset Section 0h FP_CTRL Flash Patch Control Register read write 00000260h Section 2 5 1 1 4h FP...

Page 181: ...LE r 0 r 1 r 1 r 0 r 0 r 0 w 0 rw 0 Table 2 98 FP_CTRL Register Field Descriptions Bit Field Type Reset Description 31 14 RESERVED R 0h 13 12 NUM_CODE2 R 0h Number of full banks of code comparators si...

Page 182: ...allocated to each of the eight FPB comparators A comparison match remaps to 3 b001 REMAP COMP 2 0 HADDR 1 0 where 3 b001 hardwires the remapped access to system space REMAP is the 24 bit 8 word aligne...

Page 183: ...P_COMP0 Register Field Descriptions Bit Field Type Reset Description 31 30 REPLACE R W Undefined This selects what happens when the COMP address is matched Settings other than b00 are only valid for i...

Page 184: ...FP_COMP1 Register Field Descriptions Bit Field Type Reset Description 31 30 REPLACE R W Undefined This selects what happens when the COMP address is matched Settings other than b00 are only valid for...

Page 185: ...2 FP_COMP2 Register Field Descriptions Bit Field Type Reset Description 31 30 REPLACE R W Undefined This selects what happens when the COMP address is matched Settings other than b00 are only valid fo...

Page 186: ...3 FP_COMP3 Register Field Descriptions Bit Field Type Reset Description 31 30 REPLACE R W Undefined This selects what happens when the COMP address is matched Settings other than b00 are only valid fo...

Page 187: ...4 FP_COMP4 Register Field Descriptions Bit Field Type Reset Description 31 30 REPLACE R W Undefined This selects what happens when the COMP address is matched Settings other than b00 are only valid fo...

Page 188: ...FP_COMP5 Register Field Descriptions Bit Field Type Reset Description 31 30 REPLACE R W Undefined This selects what happens when the COMP address is matched Settings other than b00 are only valid for...

Page 189: ...6 FP_COMP6 Register Field Descriptions Bit Field Type Reset Description 31 30 REPLACE R W Undefined This selects what happens when the COMP address is matched Settings other than b00 are only valid fo...

Page 190: ...7 FP_COMP7 Register Field Descriptions Bit Field Type Reset Description 31 30 REPLACE R W Undefined This selects what happens when the COMP address is matched Settings other than b00 are only valid fo...

Page 191: ...WT LSU Count Register read write Undefined Section 2 5 2 6 18h FOLDCNT DWT Fold Count Register read write Undefined Section 2 5 2 7 1Ch PCSR DWT Program Counter Sample Register read only Undefined Sec...

Page 192: ...NA R W 0h Enables Cycle count event Emits an event when the POSTCNT counter triggers it See CYCTAP bit 9 and POSTPRESET bits 4 1 for details This event is only emitted if PCSAMPLENA bit 12 is disabled...

Page 193: ...econd or less by selecting a tap on the DWT_CYCCNT register To use synchronization heartbeat and hot connect synchronization CYCCNTENA must be set to 1 SYNCTAP must be set to one of its values and SYN...

Page 194: ...PLENA is clear an event is emitted when the selected tapped bit changes value 0 to 1 or 1 to 0 and any post scalar value counts to 0 3 Applications and debuggers can use the counter to measure elapsed...

Page 195: ...CNT Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED CPICNT r r r r r r r r r r r r r r r r r r r r r r r r rw rw rw rw rw rw rw rw Table 2 111 C...

Page 196: ...t processing Figure 2 100 EXCCNT Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED EXCCNT r r r r r r r r r r r r r r r r r r r r r r r r rw rw rw...

Page 197: ...18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED SLEEPCNT r r r r r r r r r r r r r r r r r r r r r r r r rw rw rw rw rw rw rw rw Table 2 113 SLEEPCNT Register Field Descriptions Bit Field Type...

Page 198: ...23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED LSUCNT r r r r r r r r r r r r r r r r r r r r r r r r rw rw rw rw rw rw rw rw Table 2 114 LSUCNT Register Field Descriptions Bi...

Page 199: ...t Register to count the total number of folded instructions This counts 1 for each instruction that takes 0 cycles Figure 2 103 FOLDCNT Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 1...

Page 200: ...filing using a debug agent without changing the currently executing code If the core is not in debug state the value returned is the instruction address of a recently executed instruction If the core...

Page 201: ...Registers 0 3 to write the values that trigger watchpoint events Figure 2 105 COMP0 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 COMP rw rw rw rw rw r...

Page 202: ...27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED MASK r r r r r r r r r r r r r r r r r r r r r r r r r r r r rw rw rw rw Table 2 118 MASK0 Register Field Description...

Page 203: ...2 119 FUNCTION0 Register Field Descriptions Bit Field Type Reset Description 31 25 RESERVED R 0h 24 MATCHED R 0h This bit is set when the comparator matches and indicates that the operation defined b...

Page 204: ...dress offset through ITM 10b R W EMITRANGE 0 emit data through ITM on read and write EMITRANGE 1 emit data and address offset through ITM on read or write 11b R W EMITRANGE 0 sample PC and data value...

Page 205: ...arator Register 1 Use the DWT Comparator Registers 0 3 to write the values that trigger watchpoint events Figure 2 108 COMP1 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10...

Page 206: ...27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED MASK r r r r r r r r r r r r r r r r r r r r r r r r r r r r rw rw rw rw Table 2 121 MASK1 Register Field Description...

Page 207: ...RESERVED EMITRANGE RESERVED FUNCTION rw 0 r 0 rw 0 r 0 rw 0 rw 0 rw 0 rw 0 Table 2 122 FUNCTION1 Register Field Descriptions Bit Field Type Reset Description 31 25 RESERVED R 0h 24 MATCHED R 0h This b...

Page 208: ...WT_FUNCTION1 This means that the data matching functionality is not available in the implementation Test the availability of data matching by writing and reading the DATAVMATCH bit in DWT_FUNCTION1 If...

Page 209: ...arator Register 2 Use the DWT Comparator Registers 0 3 to write the values that trigger watchpoint events Figure 2 111 COMP2 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10...

Page 210: ...27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED MASK r r r r r r r r r r r r r r r r r r r r r r r r r r r r rw rw rw rw Table 2 124 MASK2 Register Field Description...

Page 211: ...2 125 FUNCTION2 Register Field Descriptions Bit Field Type Reset Description 31 25 RESERVED R 0h 24 MATCHED R 0h This bit is set when the comparator matches and indicates that the operation defined b...

Page 212: ...dress offset through ITM 10b R W EMITRANGE 0 emit data through ITM on read and write EMITRANGE 1 emit data and address offset through ITM on read or write 11b R W EMITRANGE 0 sample PC and data value...

Page 213: ...arator Register 3 Use the DWT Comparator Registers 0 3 to write the values that trigger watchpoint events Figure 2 114 COMP3 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10...

Page 214: ...27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED MASK r r r r r r r r r r r r r r r r r r r r r r r r r r r r rw rw rw rw Table 2 127 MASK3 Register Field Description...

Page 215: ...2 128 FUNCTION3 Register Field Descriptions Bit Field Type Reset Description 31 25 RESERVED R 0h 24 MATCHED R 0h This bit is set when the comparator matches and indicates that the operation defined b...

Page 216: ...dress offset through ITM 10b R W EMITRANGE 0 emit data through ITM on read and write EMITRANGE 1 emit data and address offset through ITM on read or write 11b R W EMITRANGE 0 sample PC and data value...

Page 217: ...5 ITM Stimulus Port 15 read write Undefined Section 2 5 3 16 40h STIM16 ITM Stimulus Port 16 read write Undefined Section 2 5 3 17 44h STIM17 ITM Stimulus Port 17 read write Undefined Section 2 5 3 18...

Page 218: ...ace does not provide an atomic read modify write so you must use the Cortex M4 exclusive monitor if a polled printf is used concurrently with ITM usage by interrupts or other threads Figure 2 117 STIM...

Page 219: ...does not provide an atomic read modify write so you must use the Cortex M4 exclusive monitor if a polled printf is used concurrently with ITM usage by interrupts or other threads Figure 2 118 STIM1 Re...

Page 220: ...does not provide an atomic read modify write so you must use the Cortex M4 exclusive monitor if a polled printf is used concurrently with ITM usage by interrupts or other threads Figure 2 119 STIM2 Re...

Page 221: ...does not provide an atomic read modify write so you must use the Cortex M4 exclusive monitor if a polled printf is used concurrently with ITM usage by interrupts or other threads Figure 2 120 STIM3 Re...

Page 222: ...does not provide an atomic read modify write so you must use the Cortex M4 exclusive monitor if a polled printf is used concurrently with ITM usage by interrupts or other threads Figure 2 121 STIM4 R...

Page 223: ...does not provide an atomic read modify write so you must use the Cortex M4 exclusive monitor if a polled printf is used concurrently with ITM usage by interrupts or other threads Figure 2 122 STIM5 R...

Page 224: ...does not provide an atomic read modify write so you must use the Cortex M4 exclusive monitor if a polled printf is used concurrently with ITM usage by interrupts or other threads Figure 2 123 STIM6 R...

Page 225: ...does not provide an atomic read modify write so you must use the Cortex M4 exclusive monitor if a polled printf is used concurrently with ITM usage by interrupts or other threads Figure 2 124 STIM7 R...

Page 226: ...does not provide an atomic read modify write so you must use the Cortex M4 exclusive monitor if a polled printf is used concurrently with ITM usage by interrupts or other threads Figure 2 125 STIM8 R...

Page 227: ...does not provide an atomic read modify write so you must use the Cortex M4 exclusive monitor if a polled printf is used concurrently with ITM usage by interrupts or other threads Figure 2 126 STIM9 R...

Page 228: ...e does not provide an atomic read modify write so you must use the Cortex M4 exclusive monitor if a polled printf is used concurrently with ITM usage by interrupts or other threads Figure 2 127 STIM10...

Page 229: ...e does not provide an atomic read modify write so you must use the Cortex M4 exclusive monitor if a polled printf is used concurrently with ITM usage by interrupts or other threads Figure 2 128 STIM11...

Page 230: ...e does not provide an atomic read modify write so you must use the Cortex M4 exclusive monitor if a polled printf is used concurrently with ITM usage by interrupts or other threads Figure 2 129 STIM12...

Page 231: ...e does not provide an atomic read modify write so you must use the Cortex M4 exclusive monitor if a polled printf is used concurrently with ITM usage by interrupts or other threads Figure 2 130 STIM13...

Page 232: ...e does not provide an atomic read modify write so you must use the Cortex M4 exclusive monitor if a polled printf is used concurrently with ITM usage by interrupts or other threads Figure 2 131 STIM14...

Page 233: ...e does not provide an atomic read modify write so you must use the Cortex M4 exclusive monitor if a polled printf is used concurrently with ITM usage by interrupts or other threads Figure 2 132 STIM15...

Page 234: ...e does not provide an atomic read modify write so you must use the Cortex M4 exclusive monitor if a polled printf is used concurrently with ITM usage by interrupts or other threads Figure 2 133 STIM16...

Page 235: ...e does not provide an atomic read modify write so you must use the Cortex M4 exclusive monitor if a polled printf is used concurrently with ITM usage by interrupts or other threads Figure 2 134 STIM17...

Page 236: ...e does not provide an atomic read modify write so you must use the Cortex M4 exclusive monitor if a polled printf is used concurrently with ITM usage by interrupts or other threads Figure 2 135 STIM18...

Page 237: ...e does not provide an atomic read modify write so you must use the Cortex M4 exclusive monitor if a polled printf is used concurrently with ITM usage by interrupts or other threads Figure 2 136 STIM19...

Page 238: ...e does not provide an atomic read modify write so you must use the Cortex M4 exclusive monitor if a polled printf is used concurrently with ITM usage by interrupts or other threads Figure 2 137 STIM20...

Page 239: ...e does not provide an atomic read modify write so you must use the Cortex M4 exclusive monitor if a polled printf is used concurrently with ITM usage by interrupts or other threads Figure 2 138 STIM21...

Page 240: ...e does not provide an atomic read modify write so you must use the Cortex M4 exclusive monitor if a polled printf is used concurrently with ITM usage by interrupts or other threads Figure 2 139 STIM22...

Page 241: ...e does not provide an atomic read modify write so you must use the Cortex M4 exclusive monitor if a polled printf is used concurrently with ITM usage by interrupts or other threads Figure 2 140 STIM23...

Page 242: ...e does not provide an atomic read modify write so you must use the Cortex M4 exclusive monitor if a polled printf is used concurrently with ITM usage by interrupts or other threads Figure 2 141 STIM24...

Page 243: ...e does not provide an atomic read modify write so you must use the Cortex M4 exclusive monitor if a polled printf is used concurrently with ITM usage by interrupts or other threads Figure 2 142 STIM25...

Page 244: ...e does not provide an atomic read modify write so you must use the Cortex M4 exclusive monitor if a polled printf is used concurrently with ITM usage by interrupts or other threads Figure 2 143 STIM26...

Page 245: ...e does not provide an atomic read modify write so you must use the Cortex M4 exclusive monitor if a polled printf is used concurrently with ITM usage by interrupts or other threads Figure 2 144 STIM27...

Page 246: ...e does not provide an atomic read modify write so you must use the Cortex M4 exclusive monitor if a polled printf is used concurrently with ITM usage by interrupts or other threads Figure 2 145 STIM28...

Page 247: ...e does not provide an atomic read modify write so you must use the Cortex M4 exclusive monitor if a polled printf is used concurrently with ITM usage by interrupts or other threads Figure 2 146 STIM29...

Page 248: ...e does not provide an atomic read modify write so you must use the Cortex M4 exclusive monitor if a polled printf is used concurrently with ITM usage by interrupts or other threads Figure 2 147 STIM30...

Page 249: ...e does not provide an atomic read modify write so you must use the Cortex M4 exclusive monitor if a polled printf is used concurrently with ITM usage by interrupts or other threads Figure 2 148 STIM31...

Page 250: ...16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 STIMENA R W 0h Table 2 162 TER Register Field Descriptions Bit Field Type Reset Description 31 0 STIMENA R W 0h Bit mask to enable tracing on ITM stimulus port...

Page 251: ...Type Reset Description 31 24 RESERVED R W 0h 23 BUSY R W 0h Set when ITM events present and being drained 22 16 ATBID R W 0h ATB ID for CoreSight system 15 10 RESERVED R W 0h 9 8 TSPRESCALE R W 0h TS...

Page 252: ...1 0 RESERVED ATVALIDM W 0h W 0h Table 2 165 IWR Register Field Descriptions Bit Field Type Reset Description 31 1 RESERVED W 0h 0 ATVALIDM W 0h When the integration mode is set 0 ATVALIDM clear 1 ATVA...

Page 253: ...f 0xC5ACCE55 enables more write access to Control Register 0xE00 0xFFC An invalid write removes write access 2 5 3 39 LSR Register Offset FB4h reset 00000003h LSR is shown in Figure 2 155 and describe...

Page 254: ...5 2019 Texas Instruments Incorporated Reset Controller RSTCTL Chapter 3 SLAU356I March 2015 Revised June 2019 Reset Controller RSTCTL This chapter describes the Reset Controller in MSP432P4xx devices...

Page 255: ...control over the device without completely sacrificing the device state Figure 3 1 shows the reset generation mechanism with its classes of resets The reset priority is in decreasing order from left...

Page 256: ...ce a controlled re execution of the boot code without the need to issue a complete POR As a result the debugger or user application can request a boot override mode of operation like requesting for se...

Page 257: ...e are aborted WDT module All system level bus transactions are maintained All peripheral configurations are maintained Returns control to the user code Debugger connection to the device is maintained...

Page 258: ...egister Section 3 3 7 100h RSTCTL_PSSRESET_STAT PSS Reset Status Register Section 3 3 8 104h RSTCTL_PSSRESET_CLR PSS Reset Status Clear Register Section 3 3 9 108h RSTCTL_PCMRESET_STAT PCM Reset Statu...

Page 259: ...r r r r r r r r r r r r r r r r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RSTKEY Reserved HARD _REQ SOFT _REQ w w w w w w w w r r r r r r w w Table 3 2 RSTCTL_RESET_REQ Register Description Bit Field Type...

Page 260: ...d Reset 1 14 SRC14 R 0h If 1 indicates that SRC14 was the source of the Hard Reset 1 13 SRC13 R 0h If 1 indicates that SRC13 was the source of the Hard Reset 1 12 SRC12 R 0h If 1 indicates that SRC12...

Page 261: ...CTL_HARDRESET_STAT Write 0 has no effect 11 SRC11 W 0h Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT Write 0 has no effect 10 SRC10 W 0h Write 1 clears the corresponding bit in the...

Page 262: ...TL_HARDRESET_STAT and initiates a Hard Reset Write 0 has no effect 10 SRC10 W 0h Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT and initiates a Hard Reset Write 0 has no effect 9 SRC9...

Page 263: ...t Reset 1 14 SRC14 R 0h If 1 indicates that SRC14 was the source of the Soft Reset 1 13 SRC13 R 0h If 1 indicates that SRC13 was the source of the Soft Reset 1 12 SRC12 R 0h If 1 indicates that SRC12...

Page 264: ...CTL_SOFTRESET_STAT Write 0 has no effect 11 SRC11 W 0h Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT Write 0 has no effect 10 SRC10 W 0h Write 1 clears the corresponding bit in the...

Page 265: ...TL_SOFTRESET_STAT and initiates a Soft Reset Write 0 has no effect 10 SRC10 W 0h Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT and initiates a Soft Reset Write 0 has no effect 9 SRC9...

Page 266: ...the PSS with SVSMH enabled and set as supervisor 0 Reserved R 1h Reserved NOTE The bits in this register may be set in different combinations indicating the sequence of reset events caused by the PSS...

Page 267: ...es if POR was caused by PCM due to an exit from LPM4 5 0 LPM35 R 0h Indicates if POR was caused by PCM due to an exit from LPM3 5 NOTE The bits in this register are cleared on a POR event of RSTn NMI...

Page 268: ...1 Reserved R 0h Reserved Always reads 0h 0 RSTNMI R 0h Indicates if POR was caused by RSTn NMI pin based reset event in the device This bit comes up by default as 0 in the case of cold power up This i...

Page 269: ..._REBOOTRESET_STAT Register Description Bit Field Type Reset Description 31 1 Reserved R 0h Reserved Always reads 0h 0 REBOOT R 0h Indicates if Reboot reset was caused by the SYSCTL module 3 3 15 RSTCT...

Page 270: ...t Field Type Reset Description 31 1 Reserved R 0h Reserved Always reads 0h 0 DCOR_SHT R 0h Indicates if POR was caused by DCO short circuit fault in the external resistor mode 3 3 17 RSTCTL_CSRESET_CL...

Page 271: ...e System Controller on MSP432P4xx devices Topic Page 4 1 SYSCTL Introduction 272 4 2 Device Memory Configuration and Status 272 4 3 NMI Configuration 273 4 4 Watchdog Timer Reset Configuration 273 4 5...

Page 272: ...register 4 2 2 1 SRAM Bank Enable Configuration The application can optimize the power consumption of the SRAM To enable this optimization the SRAM memory is divided into different banks that can be p...

Page 273: ...he device These NMI sources can also be configured as maskable interrupts through appropriate programming of the NVIC registers 4 4 Watchdog Timer Reset Configuration The watchdog timer module generat...

Page 274: ...to the device through the JTAG or SWD interfaces This feature is called JTAG and SWD lock To setup JTAG and SWD lock application is required to initiate a boot override sequence in the system See Sec...

Page 275: ...could be made to halt the processor and reverse engineer code contents by accessing the CPU registers with single step iterations Disabling the debugger connection whenever execution is inside a secu...

Page 276: ...ough the Secure Zone Data Unlock Register SYS_SECDATA_UNLOCK Unlock commands to the Secure Zone Data Unlock Register are honored only if the following conditions are satisfied The IP protected secure...

Page 277: ...32P4xx devices see Figure 4 2 The password shown here should be the same as the password used when enabling the JTAG and SWD lock in the boot override mailbox JTAG_SWD_LOCK_UNENC_PWD This password is...

Page 278: ...finds a boot override command Boot code checks for the authenticity by comparing the SEC_ZONEx_UNENC_PWD from the payload against the values that were provided during IP Protected secure zone setup an...

Page 279: ...Factory Reset To erase the entire flash main memory Removes all security definitions in the system The SYSCTL module implements a register level infrastructure for boot overrides These registers are...

Page 280: ...SSWD_PARTIAL0 3 on SYS_BOOTOVER_ACK All 128 bits of password received NO NO Indicate BUSY through SYS_BOOTOVER_ACK register Perform Factory Reset NO YES Factory Reset Success Indicate SUCCESS through...

Page 281: ...s a series of commands and parameters which have to be setup by the user The flash mailbox can be programmed with the appropriate values like any other flash location When the setup of the flash mailb...

Page 282: ...te Enable 0x0000000 any value other than 0xFFFFFFFF 0xB0 SEC_ZONE0_DATA_EN Disable 0xFFFFFFFF default state Enable 0x00000000 any value other than 0xFFFFFFFF 0xB4 ACK Acknowledgment for this command 0...

Page 283: ...Enable 0x0000000 any value other than 0xFFFFFFFF 0x170 SEC_ZONE2_DATA_EN Disable 0xFFFFFFFF default state Enable 0x00000000 any value other than 0xFFFFFFFF 0x174 ACK Acknowledgment for this command 0...

Page 284: ...h BIT1 2h BIT2 3h BIT3 4h BIT4 5h BIT5 6h BIT6 7h BIT7 Bits 3 0 Port to be used for HW BSL entry sequence 0h P1 1h P2 2h P3 3h Fh Reserved 0x1EC 0x1F0 Reserved 0xFFFFFFFF 0x1F4 ACK Acknowledgment for...

Page 285: ...This value should match the SEC_ZONE3_LENGTH parameter 128 bits There is a limitation that the IP protected secure zone update restricts the user to update a full secure zone User cannot initiate a pa...

Page 286: ...UPDATE 0x04000000 SEC_ZONE3_UPDATE 0x08000000 JTAG_SWD_LOCK_ENC_UPDATE 0x10000000 FACTORY_RESET_PARAMS 0x20000000 ANY_CONFIG Set the bits corresponding to any of the previous commands For example if y...

Page 287: ...ed in the mailbox to NONE and then reboots the device The device should now be secure with IP protection if the boot override ACK field has a value of 0xACE 4 8 6 2 3 Using ANY_CONFIG Command This com...

Page 288: ...TI BSL is desired 3 IP protection setup is allowed only in Bank 0 of main memory of flash 4 Hardware invocation of BSL is not supported by default Users must enable it using the boot override mailbox...

Page 289: ...Revised June 2019 Submit Documentation Feedback Copyright 2015 2019 Texas Instruments Incorporated System Controller SYSCTL 4 9 Device Descriptor Table Each device provides a data structure in memory...

Page 290: ...vice Info Tag TAG_DIEREC 0000000Ch Die Record Tag TAG_RANDNUM 0000000Dh Random Number Tag Reserved 0000000Eh Reserved for future use TAG_BSL 0000000Fh BSL Configuration Tag 4 9 2 TLV Checksum The Flet...

Page 291: ...nd external resistor modes of the DCO The DCO frequency calibration and the DCO constant values are necessary to program the DCO to any desired frequency in the supported frequency range of 1 to 48 MH...

Page 292: ...ed Word Reserved Word Reserved Word Reserved Word Reserved Word Reserved Word Reserved Word CAL_ADC_12T30 Word CAL_ADC_12T85 Word CAL_ADC_145T30 Word CAL_ADC_145T85 Word CAL_ADC_25T30 Word CAL_ADC_25T...

Page 293: ...gth 00000002h Word Maximum Programming Pulses Word Maximum Erase Pulses 4 9 3 4 Random Number Seed Table 4 8 lists the random number seed Table 4 8 Random Number Seed Random Number Tag 0000000Dh Lengt...

Page 294: ...e Peripheral ID register bit descriptions from the Arm Cortex M4 specifications See the Arm Debug interface V5 Architecture Specification for bit level details on the Arm Cortex M4 Peripheral ID regis...

Page 295: ...UNLOCK IP Protected Secure Zone Data Access Unlock Register Section 4 11 10 1000h SYS_MASTER_UNLOCK Master Unlock Register Section 4 11 11 1004h SYS_BOOTOVER_REQ0 Boot Override Request 0 Register Sect...

Page 296: ...e 4 9 SYS_REBOOT_CTL Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved r r r r r r r r r r r r r r r r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 WKEY Reserved REBO OT w w w w w w w w r r r...

Page 297: ...W 0h 0b Indicates the RSTn NMI pin was not the source of NMI 1b Indicates the RSTn NMI pin was the source of NMI 18 PCM_FLG R 0h 0b indicates the PCM interrupt was not the source of NMI 1b indicates t...

Page 298: ...r 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved r r r r r r r r r r r r r r r r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved VIOLA TION TIMEO UT r r r r r r r r r r r r r r rw 1 rw 1 Tabl...

Page 299: ...halted 11 HALT_eUB2 RW 0h 0b peripheral operation unaffected when CPU is halted 1b freezes peripheral operation when CPU is halted 10 HALT_eUB1 RW 0h 0b peripheral operation unaffected when CPU is ha...

Page 300: ...Register Figure 4 13 SYS_SRAM_SIZE Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 SIZE r r r r r r r r r r r r r r r r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SIZE r r r r r r r r r r r r r r...

Page 301: ...banks are enabled disabled according to values of bits 7 0 of this register 0b SRAM is not ready for accesses Banks are undergoing an enable or disable sequence and reads or writes to SRAM are stalled...

Page 302: ...iption Bit Field Type Reset Description 31 17 Reserved R 0h Reserved Reads return 0h 16 SRAM_RDY 1 R 0h 1b SRAM is ready for accesses All SRAM banks are enabled disabled for retention according to val...

Page 303: ...gister Figure 4 16 SYS_FLASH_SIZE Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 SIZE r r r r r r r r r r r r r r 1 r r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SIZE r r r r r r r r r r r r r r...

Page 304: ...ster Figure 4 17 SYS_DIO_GLTFLT_CTL Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved r r r r r r r r r r r r r r r r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved GLTFL T_EN r r r r...

Page 305: ...r r r r r r r r r r r r r r r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 UNLKEY rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 Table 4 21 SYS_SECDATA_UNLOCK Register Descri...

Page 306: ...9 18 17 16 Reserved r r r r r r r r r r r r r r r r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 UNLKEY rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 Table 4 22 SYS_MASTER_U...

Page 307: ...SYS_MASTER_UNLOCK register is unlocked Figure 4 20 SYS_BOOTOVER_REQ0 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 REGVAL rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 r...

Page 308: ...R_UNLOCK register is unlocked Figure 4 21 SYS_BOOTOVER_REQ1 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 REGVAL rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 r...

Page 309: ...if SYS_MASTER_UNLOCK register is unlocked Figure 4 22 SYS_BOOTOVER_ACK Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 REGVAL rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0...

Page 310: ...r r r r r r r r r r r r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 WKEY Reserved REBO OT POR w w w w w w w w r r r r r r w w Table 4 26 SYS_RESET_REQ Register Description Bit Field Type Reset Description...

Page 311: ...re for the corresponding resets only If a hard reset override is programmed the soft resets are still propagated into the system Therefore the application must program the hard and soft reset bits to...

Page 312: ...20 19 18 17 16 Reserved r r r r r r r r r r r r r r r r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved IP_PR OT_A CT JTAG_ SWD_ LOCK _ACT DBG_ SEC_ ACT Reserv ed Reserv ed Reserv ed r r r r r r r r r...

Page 313: ...cribes the System Controller A module Topic Page 5 1 SYSCTL_A Introduction 314 5 2 Device Memory Configuration and Status 314 5 3 NMI Configuration 315 5 4 Watchdog Timer Reset Configuration 315 5 5 P...

Page 314: ...flash main memory can vary from device to device in the MSP432P4xx family The flash main memory can be viewed as two independent identical banks each of which is half of the total size of the flash ma...

Page 315: ...is time and access resumes only after the SRAM banks are ready for read or write operations This is handled transparently and does not require any code intervention 5 2 2 2 SRAM Block Retention Config...

Page 316: ...the various classes of resets in the device In addition SYSCTL_A can override the device resets and initiate reset requests for debug purposes See Section 5 11 for details NOTE Reset overrides are for...

Page 317: ...unlocked for data accesses This is a configurable feature and is described in more detail in Section 5 8 4 2 Any data access that violates this requirement is considered unauthorized and returns an e...

Page 318: ...should also prevent halt conditions but malicious software may be able to enable breakpoint addresses that point into secure memory zones and thereby cause a halt when the CPU is executing secure cod...

Page 319: ...unsecure device update except that it does not work for data or code being updated into a IP protected zone flash memory For firmware or data updates to IP protected flash memory zones see Section 5...

Page 320: ...IP Protection Enabled Firmware or data load to a IP protected secure zone is done by invoking the BSL and then subsequently by invoking the boot override mode of the device The update could be either...

Page 321: ...r data to be updated 2 The payload is encrypted through an AES CBC operation 3 The encrypted payload is now transmitted through BSL into a free space in Bank 1 of the main flash memory of the device 4...

Page 322: ...em SYSCTL_A implements a register level infrastructure for the boot overrides These registers are reset only on a POR class of reset and can therefore communicate between the application and the boot...

Page 323: ...WD_PARTIAL0 3 on SYS_BOOTOVER_ACK All 128 bits of password received NO NO Indicate BUSY through SYS_BOOTOVER_ACK register Perform Factory Reset NO YES Factory Reset Success Indicate SUCCESS through SY...

Page 324: ...the boot override request command in the flash mailbox and executes the command 5 8 6 2 1 Boot Override Flash Mailbox FL_BOOTOVER_MAILBOX Table 5 1 lists the structure of the mailbox Relative addresse...

Page 325: ...tate Enable 0x0000000 Any value other than 0xFFFFFFFF 0xB0 SEC_ZONE0_DATA_EN Disable 0xFFFFFFFF default state Enable 0x00000000 Any value other than 0xFFFFFFFF 0xB4 ACK Acknowledgment for this command...

Page 326: ...te Enable 0x0000000 Any value other than 0xFFFFFFFF 0x170 SEC_ZONE2_DATA_EN Disable 0xFFFFFFFF default state Enable 0x00000000 Any value other than 0xFFFFFFFF 0x174 ACK Acknowledgment for this command...

Page 327: ...BIT7 Bits 3 0 Port to be used for HW BSL entry sequence 0h P1 1h P2 2h P3 3h Fh Reserved 0x1EC 0x1F0 Reserved 0xFFFFFFFF 0x1F4 ACK Acknowledgment for this command 0x1F8 JTAG_SWD_LOCK_ ENC_UPDATE JTAG_...

Page 328: ...he main flash memory 0x240 SEC_ZONE3_ENCPAYLOADLEN Length of the payload in bytes This value must match the SEC_ZONE3_LENGTH parameter plus 128 bits There is a limitation that the IP protected secure...

Page 329: ...to a 4KB boundary JTAG and SWD encrypted updates to the device must be done in multiples of 4KB In field updates for IP Protection to the device must be done in full size of the IP Protection block N...

Page 330: ...et up the FL_BOOTOVER_MAILBOX with the following structure MB_START 0x0115ACF6 CMD SEC_ZONE0_EN SEC_ZONE0_PARAMS ACK 0xFFFFFFFF SEC_ZONE0_PARAMS SEC_ZONE0_SECEN ENABLE SEC_ZONE0_PARAMS SEC_ZONE0_START...

Page 331: ...boot override ACK field has a value of 0xACE the device is secured with both IP protection and JTAG and SWD lock 5 8 7 Device Security and Boot Overrides User Considerations This section provides for...

Page 332: ...he device descriptor can be verified by Fletcher 32 checksum Figure 5 7 shows the logical order and structure of the device descriptor table The complete device descriptor table and its contents can b...

Page 333: ...mputed with the following code snippet and with a seed value of DADA0000h Calculates a Fletcher 32 checksum which consists of two parts The first is a checksum of the data values The second is a check...

Page 334: ...and external resistor modes of the DCO The DCO frequency calibration and the DCO constant values are necessary to program the DCO to any desired frequency in the supported frequency range of 1 to 48...

Page 335: ...Reserved Word Reserved Word Reserved Word Reserved Word Reserved Word Reserved Word CAL_ADC_12T30 Word CAL_ADC_12T85 Word CAL_ADC_145T30 Word CAL_ADC_145T85 Word CAL_ADC_25T30 Word CAL_ADC_25T85 The...

Page 336: ...ngth 00000002h Word Maximum programming pulses Word Maximum erase pulses 5 9 3 4 Random Number Seed Table 5 9 lists the random number seed Table 5 9 Random Number Seed Random Number Tag 0000000Dh Leng...

Page 337: ...the Peripheral ID register bit descriptions from the Arm Cortex M4 specifications See the Arm Debug interface V5 Architecture Specification for bit level details on the Arm Cortex M4 Peripheral ID reg...

Page 338: ...Section 5 11 14 005Ch SYS_SRAM_BANKEN_CTL3 SRAM Bank Enable Control Register 3 Section 5 11 15 0070h SYS_SRAM_BLKRET_CTL0 SRAM Block Retention Control Register 0 Section 5 11 16 0074h SYS_SRAM_BLKRET_...

Page 339: ...gure 5 10 SYS_REBOOT_CTL Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved r r r r r r r r r r r r r r r r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 WKEY Reserved REBO OT w w w w w w w w r...

Page 340: ...G RW 0h 0b Indicates the RSTn NMI pin was not the source of NMI 1b Indicates the RSTn NMI pin was the source of NMI 18 PCM_FLG R 0h 0b indicates the PCM interrupt was not the source of NMI 1b indicate...

Page 341: ...ster 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved r r r r r r r r r r r r r r r r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved VIOLA TION TIMEO UT r r r r r r r r r r r r r r rw 1 rw 1 T...

Page 342: ...eration when CPU is halted 12 HALT_eUB3 RW 0h 0b IP operation unaffected when CPU is halted 1b freezes IP operation when CPU is halted 11 HALT_eUB2 RW 0h 0b IP operation unaffected when CPU is halted...

Page 343: ...ize Register Figure 5 14 SYS_SRAM_SIZE Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 SIZE r r r r r r r r r r r r r r r r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SIZE r r r r r r r r r r r r...

Page 344: ...s Register Figure 5 15 SYS_SRAM_NUMBANKS Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 NUM r r r r r r r r r r r r r r r r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 NUM r r r r r r r r r r r r...

Page 345: ...Register Figure 5 16 SYS_SRAM_NUMBLOCKS Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 NUM r r r r r r r r r r r r r r r r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 NUM r r r r r r r r r r r r...

Page 346: ...Size Register Figure 5 17 SYS_MAINFLASH_SIZE Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 SIZE r r r r r r r r r r r r r r 1 r r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SIZE r r r r r r r r...

Page 347: ...ory Size Register Figure 5 18 SYS_INFOFLASH_SIZE Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 SIZE r r r r r r r r r r r r r r 1 r r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SIZE r r r r r r...

Page 348: ...egister Figure 5 19 SYS_DIO_GLTFLT_CTL Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved r r r r r r r r r r r r r r r r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved GLTFL T_EN r r r...

Page 349: ...r r r r r r r r r r r r r r r r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 UNLKEY rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 Table 5 23 SYS_SECDATA_UNLOCK Register Des...

Page 350: ...RW 1h 0b Disables Bank31 of the SRAM 1b Enables Bank31 of the SRAM When set to 1 bank enable bits for all banks below this bank are set to 1 as well 30 BNK30_EN 1 RW 1h 0b Disables Bank30 of the SRAM...

Page 351: ...K17_EN 1 RW 1h 0b Disables Bank17 of the SRAM 1b Enables Bank17 of the SRAM When set to 1 bank enable bits for all banks below this bank are set to 1 as well 16 BNK16_EN 1 RW 1h 0b Disables Bank16 of...

Page 352: ...sables Bank6 of the SRAM 1b Enables Bank6 of the SRAM When set to 1 bank enable bits for all banks below this bank are set to 1 as well 5 BNK5_EN 1 RW 1h 0b Disables Bank5 of the SRAM 1b Enables Bank5...

Page 353: ...are not ready and writes to this bit are ignored Table 5 25 SYS_SRAM_BANKEN_CTL1 Register Description Bit Field Type Reset Description 31 BNK63_EN 1 RW 1h 0b Disables Bank63 of the SRAM 1b Enables Ba...

Page 354: ...K50_EN 1 RW 1h 0b Disables Bank50 of the SRAM 1b Enables Bank50 of the SRAM When set to 1 bank enable bits for all banks below this bank are set to 1 as well 17 BNK49_EN 1 RW 1h 0b Disables Bank49 of...

Page 355: ...NK38_EN 1 RW 1h 0b Disables Bank38 of the SRAM 1b Enables Bank38 of the SRAM When set to 1 bank enable bits for all banks below this bank are set to 1 as well 5 BNK37_EN 1 RW 1h 0b Disables Bank37 of...

Page 356: ...are not ready and writes to this bit are ignored Table 5 26 SYS_SRAM_BANKEN_CTL2 Register Description Bit Field Type Reset Description 31 BNK95_EN 1 RW 1h 0b Disables Bank95 of the SRAM 1b Enables Ba...

Page 357: ...K82_EN 1 RW 1h 0b Disables Bank82 of the SRAM 1b Enables Bank82 of the SRAM When set to 1 bank enable bits for all banks below this bank are set to 1 as well 17 BNK81_EN 1 RW 1h 0b Disables Bank81 of...

Page 358: ...NK70_EN 1 RW 1h 0b Disables Bank70 of the SRAM 1b Enables Bank70 of the SRAM When set to 1 bank enable bits for all banks below this bank are set to 1 as well 5 BNK69_EN 1 RW 1h 0b Disables Bank69 of...

Page 359: ...ks are not ready and writes to this bit are ignored Table 5 27 SYS_SRAM_BANKEN_CTL3 Register Description Bit Field Type Reset Description 31 BNK127_EN 1 RW 1h 0b Disables Bank127 of the SRAM 1b Enable...

Page 360: ...EN 1 RW 1h 0b Disables Bank114 of the SRAM 1b Enables Bank114 of the SRAM When set to 1 bank enable bits for all banks below this bank are set to 1 as well 17 BNK113_EN 1 RW 1h 0b Disables Bank113 of...

Page 361: ...BNK102_EN 1 RW 1h 0b Disables Bank102 of the SRAM 1b Enables Bank102 of the SRAM When set to 1 bank enable bits for all banks below this bank are set to 1 as well 5 BNK101_EN 1 RW 1h 0b Disables Bank1...

Page 362: ...ock30 of the SRAM is not retained in LPM3 or LPM4 1b Block30 of the SRAM is retained in LPM3 and LPM4 29 BLK29_RET 1 2 RW 1h 0b Block29 of the SRAM is not retained in LPM3 or LPM4 1b Block29 of the SR...

Page 363: ...is not retained in LPM3 or LPM4 1b Block10 of the SRAM is retained in LPM3 and LPM4 9 BLK9_RET 1 2 RW 1h 0b Block9 of the SRAM is not retained in LPM3 or LPM4 1b Block9 of the SRAM is retained in LPM...

Page 364: ...cription Bit Field Type Reset Description 31 BLK63_RET 1 2 RW 1h 0b Block63 of the SRAM is not retained in LPM3 or LPM4 1b Block63 of the SRAM is retained in LPM3 and LPM4 30 BLK62_RET 1 2 RW 1h 0b Bl...

Page 365: ...Block43 of the SRAM is retained in LPM3 and LPM4 10 BLK42_RET 1 2 RW 1h 0b Block42 of the SRAM is not retained in LPM3 or LPM4 1b Block42 of the SRAM is retained in LPM3 and LPM4 9 BLK41_RET 1 2 RW 1h...

Page 366: ...cription Bit Field Type Reset Description 31 BLK95_RET 1 2 RW 1h 0b Block95 of the SRAM is not retained in LPM3 or LPM4 1b Block95 of the SRAM is retained in LPM3 and LPM4 30 BLK94_RET 1 2 RW 1h 0b Bl...

Page 367: ...Block75 of the SRAM is retained in LPM3 and LPM4 10 BLK74_RET 1 2 RW 1h 0b Block74 of the SRAM is not retained in LPM3 or LPM4 1b Block74 of the SRAM is retained in LPM3 and LPM4 9 BLK73_RET 1 2 RW 1h...

Page 368: ...on Bit Field Type Reset Description 31 BLK127_RET 1 2 RW 1h 0b Block127 of the SRAM is not retained in LPM3 or LPM4 1b Block127 of the SRAM is retained in LPM3 and LPM4 30 BLK126_RET 1 2 RW 1h 0b Bloc...

Page 369: ...Block107 of the SRAM is retained in LPM3 and LPM4 10 BLK106_RET 1 2 RW 1h 0b Block106 of the SRAM is not retained in LPM3 or LPM4 1b Block106 of the SRAM is retained in LPM3 and LPM4 9 BLK105_RET 1 2...

Page 370: ...automatically set to 0 whenever any of the SYS_SRAM_BANKEN_CTLx register bits are changed It is set to 1 again after the SRAM controller has recognized the new BNKx_EN values Table 5 32 SYS_SRAM_STAT...

Page 371: ...0 19 18 17 16 Reserved r r r r r r r r r r r r r r r r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 UNLKEY rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 Table 5 33 SYS_MASTE...

Page 372: ...if SYS_MASTER_UNLOCK register is unlocked Figure 5 31 SYS_BOOTOVER_REQ0 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 REGVAL rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw...

Page 373: ...STER_UNLOCK register is unlocked Figure 5 32 SYS_BOOTOVER_REQ1 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 REGVAL rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw...

Page 374: ...nly if SYS_MASTER_UNLOCK register is unlocked Figure 5 33 SYS_BOOTOVER_ACK Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 REGVAL rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 r...

Page 375: ...r r r r r r r r r r r r r r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 WKEY Reserved REBO OT POR w w w w w w w w r r r r r r w w Table 5 37 SYS_RESET_REQ Register Description Bit Field Type Reset Descripti...

Page 376: ...ides are for the corresponding resets only If a hard reset override is programmed the soft resets are still propagated into the system Therefore the application must program the hard and soft reset bi...

Page 377: ...21 20 19 18 17 16 Reserved r r r r r r r r r r r r r r r r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved IP_PR OT_A CT JTAG_ SWD_ LOCK _ACT DBG_ SEC_ ACT Reserv ed Reserv ed Reserv ed r r r r r r r r...

Page 378: ...ght 2015 2019 Texas Instruments Incorporated Clock System CS Chapter 6 SLAU356I March 2015 Revised June 2019 Clock System CS This chapter describes the operation of the clock system Topic Page 6 1 Clo...

Page 379: ...requency SYSOSC Internal oscillator with 5 MHz typical frequency Five primary system clock signals are available from the clock module ACLK Auxiliary clock ACLK is software selectable as LFXTCLK VLOCL...

Page 380: ...t HSMCLK conditional request SMCLK_EN SMCLK unconditional request SMCLK conditional request MCLK_EN MCLK unconditional request MCLK conditional request REFO REFO VLO REFO MODOSC LFXTCLK 0 1 LFXTCLK un...

Page 381: ...ties Clock stability over operating temperature and supply voltage Low cost applications with less constrained clock accuracy requirements for example crystal less operation The CS module addresses th...

Page 382: ...ge of operation as show in Table 6 1 when HFXT operates with external crystals The HFXTDRIVE bit selects the drive capability of HFXT The HFXTDRIVE bit must be set to 0 for 1 MHz to 4 MHz operation HF...

Page 383: ...illator after LPM3 5 or LPM4 5 wakeup When the device wakes up from LPM3 5 or LPM4 5 mode all clock settings for example clock selections and dividers that were programmed before entry into these low...

Page 384: ...onal request active LFXTCLK is a source for ACLK SELAx 0 and LFXTIFG is set due to crystal oscillator fault LFXTCLK is a source for BCLK SELB 0 and LFXTIFG is set due to crystal oscillator fault LFXTC...

Page 385: ...ny module available in active mode or LPM0 mode and any MODCLK unconditional request active For LPM3 or LPM4 or LPM3 5 or LPM4 5 mode MODOSC is not available and is disabled MODOSC_EN has no effect 6...

Page 386: ...hereby forming a short circuit condition either while configuring DCO in external resistor mode DCORES 0 to 1 or during run time when DCO is operating in external resistor mode a POR reset is triggere...

Page 387: ...however a settling time is required by the DCO before the final selected frequency is obtained There is an inbuilt delay counter in the Clock System that prevents the clocks to propagate into the syst...

Page 388: ...MCLK_module_n HSMCLK_REQEN_module_n HSMCLK selected module_n enabled HSMCLK ACLK_module_y ACLK unconditional request module_y SMCLK_module_y SMCLK unconditional request module_y HSMCLK_module_y HSMCLK...

Page 389: ...re enable it if that system clock is desired Due to the clock request feature care must be taken in the application when entering low power modes to save power Although the device is programmed to en...

Page 390: ...CLK or LFXTCLK and a fault is detected the system clock is automatically switched to REFO for its clock source The REFO clock in fail safe mode of operation always runs at 32 768 kHz and the REFOFSEL...

Page 391: ...ssed before the LFXT_OscFault signal is cleared The counter can be programmed from 4096 to 32768 counts using the FCNTLF bits The default is the maximum count Any crystal fault restarts the counter It...

Page 392: ...s ready by polling the ACLK_READY in the CSSTAT register and then initiate the SELA change to LFXT Then ACLK_READY bit can be polled again to ascertain that ACLK is sourced out of LFXT This is to ensu...

Page 393: ...gister Read write Word 0000_0033h Section 6 3 3 0Ch CSCTL2 Control 2 Register Read write Word 0001_0003h Section 6 3 4 10h CSCTL3 Control 3 Register Read write Word 0000_00BBh Section 6 3 5 30h CSCLKE...

Page 394: ...ved r 0 r 0 r 0 r 0 r 0 r 0 r 0 r 0 15 14 13 12 11 10 9 8 CSKEY rw 1 rw 0 rw 1 rw 0 rw 0 rw 1 rw 0 rw 1 7 6 5 4 3 2 1 0 CSKEY rw 1 rw 0 rw 0 rw 1 rw 0 rw 1 rw 1 rw 0 Table 6 3 CSKEY Register Descripti...

Page 395: ...sabled 1b DCO is on 22 DCORES RW 0h Enables the DCO external resistor mode 0b Internal resistor mode 1b External resistor mode 21 19 Reserved R 0h Reserved Always reads as 0 18 16 DCORSEL RW 1h DCO fr...

Page 396: ...ved SELM r 0 rw 0 rw 1 rw 1 r 0 rw 0 rw 1 rw 1 Table 6 5 CSCTL1 Register Description Bit Field Type Reset Description 31 Reserved R 0h Reserved Always reads as 0 30 28 DIVS RW 0h SMCLK source divider...

Page 397: ...s as 0 10 8 SELA RW 0h Selects the ACLK source 000b LFXTCLK 001b VLOCLK 010b REFOCLK 011b 111b Reserved for future use Defaults to REFOCLK Not recommended for use to ensure future compatibilities 7 Re...

Page 398: ...on if it is used as a source for MCLK HSMCLK or SMCLK and is selected via the port selection and not in bypass mode of operation 1b HFXT is on if HFXT is selected via the port selection and HFXT is no...

Page 399: ...elected via the port selection and not in bypass mode of operation 1b LFXT is on if LFXT is selected via the port selection and LFXT is not in bypass mode of operation 7 Reserved RW 0h Reserved Must b...

Page 400: ...XT 0b Startup fault counter disabled Counter is cleared 1b Startup fault counter enabled 6 RFCNTHF W 0h Reset start fault counter for HFXT Write 1 only Self clears once written 0b Not applicable Alway...

Page 401: ...it is used as a source for ACLK MCLK HSMCLK or SMCLK 1b MODOSC is on 9 REFO_EN RW 0h Turns on the REFO oscillator regardless if used as a clock resource 0b REFO is on only if it is used as a source fo...

Page 402: ...ADY R 0h BCLK Ready status This bit indicates whether the clock is stable after a change in the frequency settings 0b Not ready 1b Ready 27 SMCLK_READY R 0h SMCLK Ready status This bit indicates wheth...

Page 403: ...ctive 17 MCLK_ON R 0h MCLK system clock status 0b Inactive 1b Active 16 ACLK_ON R 0h ACLK system clock status 0b Inactive 1b Active 15 8 Reserved R 0h Reserved Always reads as 0 7 REFO_ON R 0h REFO st...

Page 404: ...0 rw 0 rw 0 Table 6 10 CSIE Register Description Bit Field Type Reset Description 31 10 Reserved R 0h Reserved Always reads as 0 9 FCNTHFIE RW 0h Start fault counter interrupt enable HFXT 0b Interrup...

Page 405: ...lways reads as 0 6 DCOR_OPNIFG R 0h DCO external resistor open circuit fault flag DCOR_OPNIFG can be cleared via software by CLR_DCORIFG If the fault condition still remains DCOR_OPNIFG is set again 0...

Page 406: ...Field Type Reset Description 31 10 Reserved W 0h Reserved Always reads as 0 9 CLR_FCNTHFIFG W 0h Start fault counter clear interrupt flag HFXT Does not clear FCNTIFG 0b No effect 1b Clear pending int...

Page 407: ...w1 w1 w1 w1 w1 w1 Table 6 13 CSSETIFG Register Description Bit Field Type Reset Description 31 10 Reserved W 0h Reserved Always reads as 0 9 SET_FCNTHFIFG W 0h Start fault counter set interrupt flag H...

Page 408: ...30 29 28 27 26 25 24 Reserved DCO_FCAL_RSEL04 r 0 r 0 r 0 r 0 r 0 r 0 rw 0 rw 1 23 22 21 20 19 18 17 16 DCO_FCAL_RSEL04 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 15 14 13 12 11 10 9 8 Reserved r 0 r 0 r...

Page 409: ...frequency range DCORSEL 5 Figure 6 17 CSDCOERCAL1 Register 31 30 29 28 27 26 25 24 Reserved r 0 r 0 r 0 r 0 r 0 r 0 r 0 r 0 23 22 21 20 19 18 17 16 Reserved r 0 r 0 r 0 r 0 r 0 r 0 r 0 r 0 15 14 13 12...

Page 410: ...exas Instruments Incorporated Power Supply System PSS Chapter 7 SLAU356I March 2015 Revised June 2019 Power Supply System PSS This chapter describes the operation of the Power Supply System PSS Topic...

Page 411: ...VCC are shorted on the board or generated from the same source and no level shifting or isolation is done between these two supplies The VCORE output is maintained using a dedicated voltage reference...

Page 412: ...F bit a delay element masks the interrupt and reset sources until the SVSMH circuit has settled as indicated in the SVSMH on off delay time in the device specific data sheet The SVSMH module has confi...

Page 413: ...p VCC threshold voltage of 1 65 V 7 2 2 Supply Voltage Supervisor During Power up When the device is powering up the SVSMH function is enabled by default as supervisor Initially VCC is low and therefo...

Page 414: ...of a sudden failure of supply at a rate faster than recommended for SVSMH module the VCCDET generates a POR reset As described earlier this does not ensure a controlled power down of the device rather...

Page 415: ...is given in Table 7 1 Table 7 1 PSS Registers Offset Acronym Register Name Section 00h PSSKEY Key Register Section 7 3 1 04h PSSCTL0 Control 0 Register Section 7 3 2 34h PSSIE Interrupt Enable Regist...

Page 416: ...0 r 0 23 22 21 20 19 18 17 16 Reserved r 0 r 0 r 0 r 0 r 0 r 0 r 0 r 0 15 14 13 12 11 10 9 8 PSSKEY rw 1 rw 0 rw 1 rw 0 rw 0 rw 1 rw 0 rw 1 7 6 5 4 3 2 1 0 PSSKEY rw 1 rw 0 rw 0 rw 1 rw 0 rw 1 rw 1 rw...

Page 417: ...egulator operation not forced Automatic fail safe mechanism switches the core voltage regulator from DC DC to LDO when the supply voltage falls below the minimum supply voltage necessary for DC DC ope...

Page 418: ...ficient time has elapsed since enabling of the module until entry into the device low power mode to allow for successful wakeup of SVSMH module as per SVSMH on off delay time spec in respective device...

Page 419: ...0 r 0 r 0 r 0 15 14 13 12 11 10 9 8 Reserved r 0 r 0 r 0 r 0 r 0 r 0 r 0 r 0 7 6 5 4 3 2 1 0 Reserved SVSMHIE Reserved r0 r0 r0 r0 r0 r0 rw 0 r 0 Table 7 4 PSSIE Register Description Bit Field Type R...

Page 420: ...d r0 r0 r0 r0 r0 r 0 r 0 r 0 Table 7 5 PSSIFG Register Description Bit Field Type Reset Description 31 2 Reserved R 0h Reserved Always read 0 1 SVSMHIFG R 0h High side SVSM interrupt flag SVSMH 0 supe...

Page 421: ...26 25 24 Reserved r 0 r 0 r 0 r 0 r 0 r 0 r 0 r 0 23 22 21 20 19 18 17 16 Reserved r 0 r 0 r 0 r 0 r 0 r 0 r 0 r 0 15 14 13 12 11 10 9 8 Reserved r 0 r 0 r 0 r 0 r 0 r 0 r 0 r 0 7 6 5 4 3 2 1 0 Reser...

Page 422: ...8 10 Power Mode Transition Checks 437 8 11 Power Mode Clock Checks 437 8 12 Clock Configuration Changes 438 8 13 Changing Active Modes 438 8 14 Entering LPM0 Modes 440 8 15 Exiting LPM0 Modes 440 8 16...

Page 423: ...vice This includes existing conditions from the clock system CS settings and the power supply system PSS settings It is possible that a power mode request cannot be safely entered based on existing co...

Page 424: ...ased DC DC regulator in addition to a LDO to regulate the core voltage See the device specific data sheet for the availability of DC DC regulator on the device The DC DC provides increased efficiency...

Page 425: ...modes useful for low frequency operation These low frequency active modes limit the maximum frequency of operation to 128 kHz The application must not perform flash program or erase operations or any...

Page 426: ...e operation to 128 kHz Most of the peripherals are functional from the low frequency internal clock sources LFXT REFO and VLO or low frequency external clocks maximum of 128 kHz while in LPM3 In LPM4...

Page 427: ...k sources LFXT REFO and VLO can be active AM_LF_VCORE1 All high frequency clock sources must be disabled by application Flash memory and all enabled SRAM banks are active Flash erase and program opera...

Page 428: ...age level 0 or 1 Achieved by entering LPM3 with RTC and WDT modules disabled CPU is inactive with no peripheral functionality All peripherals and retention enabled SRAM banks are kept under state rete...

Page 429: ...clock sources need to be disabled by application Flash memory and all enabled SRAM banks are active Flash erase and program operations and SRAM bank enable or retention enable configuration changes mu...

Page 430: ...eing active Analog modules not requiring a clock can remain operational in this mode CPU is inactive with no peripheral functionality All other peripherals and retention enabled SRAM banks and blocks...

Page 431: ...ugh application programming Upon defined wake up events the device returns to the active mode from which the specific low power mode was entered Only for LPM3 5 and LPM4 5 modes the device always ente...

Page 432: ...e has a corresponding LPM0 mode LPM0 mode is always entered at the same core voltage level setting as the active mode at the time of LPM0 entry For example LPM0 entry from AM_LDO_VCORE0 which has a co...

Page 433: ...he application must not attempt a LPM3 or LPM4 entry from AM_DCDC_VCOREx modes Attempting this transition results in the LPM_INVALID_TR_IFG being set and the transition to be aborted by the PCM Exitin...

Page 434: ...ent voltage to the CPU could produce unpredictable results or result in a POR After requesting a power mode with a higher VCORE level when the current power mode uses a lower VCORE level there is a de...

Page 435: ...EPRI the interrupt causes the processor to wake from sleep and interrupt execution to occur If the interrupt request priority is lower than the current base priority the processor remains asleep and n...

Page 436: ...lection Table 8 3 summarizes the various power modes available the appropriate PCMCTL0 settings and the entry mechanism for each of the modes 1 X don t care Table 8 3 Power Mode Selection 1 Mode Descr...

Page 437: ...frequency or condition checks during any active or LPM0 power mode transitions The application must ensure that the system conditions are met before the transition between these mode transitions For...

Page 438: ...ive mode to the requested active mode In general there are minimum supply maximum frequency and required flash wait state requirements for the corresponding frequency of operation for each active mode...

Page 439: ...Texas Instruments Incorporated Power Control Manager PCM Figure 8 7 Active Mode Transition Flow 8 13 1 DC DC Error Checking When using the DC DC regulator there may be situations where the regulator c...

Page 440: ...applications the setting of these registers is rather infrequent and in some cases only a one time setup is necessary The basic procedure is as follows 1 The application selects sleep mode by writing...

Page 441: ...ult in the system being in an indeterministic state NOTE Clocks brought out on device pins also cause clock requests to the respective clocks in the device The application should therefore treat these...

Page 442: ...on the device by removing supply power Because the supply voltage is removed from the circuitry most register contents and SRAM contents are lost For LPM3 5 the only modules available are the RTC and...

Page 443: ...nd LPM4 5 modes should be restored to the values before entering LPM3 5 and LPM4 5 modes If LPM3 5 was entered the RTC interrupt configuration that was not retained in LPM3 5 should also be restored t...

Page 444: ...ported only in full performance mode on devices that support extended junction temperatures up to 125 C See the device specific data sheet for details 8 23 Low Power Reset In battery operated applicat...

Page 445: ...either the WFI or WFE instruction or for the case of sleep on exit at the first instruction after the return of the last pending interrupt Stepping or running through simply re execute the same instru...

Page 446: ...itor mode PSS 4 Enabled interrupt Yes Yes Yes Debugger power up request SYSPWRUPREQ event Yes Yes Yes Yes Debugger reset request DBGRSTREQ event 5 6 Yes Yes Yes Yes Yes RSTn at device pin External res...

Page 447: ...cts like a POR reset and will take the device to AM_LDO_VCORE0 configuration regardless of the mode from which the low power mode was entered 8 LOCKLPM5 bit in case of LPM4 5 mode and both LOCKLPM5 an...

Page 448: ...Name Type Reset Section 00h PCMCTL0 Control 0 Register Read write A5960000h Section 8 26 1 04h PCMCTL1 Control 1 Register Read write A5960000h Section 8 26 2 08h PCMIE Interrupt Enable register Read w...

Page 449: ...cess half word or byte access will be ignored by PCM 15 14 Reserved R 0h Reserved Always read as 0 13 8 CPM R 0h Current Power Mode These bits reflect the current power mode and will be updated once t...

Page 450: ...of the PCMCTL1 0h LPM3 Core voltage setting is similar to the mode from which LPM3 is entered 1h 9h Reserved 1 Ah LPM3 5 Core voltage setting 0 Bh Reserved 1 Ch LPM4 5 Dh Fh Reserved 1 3 0 AMR RW 0h A...

Page 451: ...to the PCMCTL0 or Clock System registers are ignored while PMR_BUSY 1 Reads to the PCMCTL0 or Clock System registers are possible while PMR_BUSY 1 7 3 Reserved R 0h Reserved Reads back 0 2 FORCE_LPM_E...

Page 452: ...0 LOCKLPM5 RW 0h Lock LPM5 This bit once set can only be cleared by the user or by a power cycle This bit is automatically set upon LPM3 5 LPM4 5 entry User cannot set this bit In the write mode this...

Page 453: ...back 0 6 DCDC_ERROR _IE RW 0h DC DC error interrupt enable Setting this bit enables an interrupt NMI when DC DC operation cannot be achieved or maintained 0b Disabled 1b Enabled 5 3 Reserved R 0h Res...

Page 454: ...it Field Type Reset Description 31 7 Reserved R 0h Reserved Reads back 0 6 DCDC_ERROR_IFG R 0h DC DC error flag This flag is set if DC DC operation cannot be achieved or maintained Flag will remain se...

Page 455: ...1 0 Reserved CLR_DCDC_E RROR_IFG Reserved CLR_AM_INVA LID_TR_IFG CLR_LPM_INV ALID_CLK_IFG CLR_LPM_INV ALID_TR_IFG w1 w1 w1 w1 w1 w1 w1 w1 Table 8 17 PCMCLRIFG Register Description Bit Field Type Reset...

Page 456: ...corporated Flash Controller FLCTL Chapter 9 SLAU356I March 2015 Revised June 2019 Flash Controller FLCTL This chapter describes the flash controller Topic Page 9 1 Introduction 457 9 2 Common Operatio...

Page 457: ...CU which has 256KB of flash main memory and 16KB of information memory Main Memory 256 KB mapped from 0h through 3_FFFFh Accesses from 0h through 1_FFFFh are mapped to Bank0 All Bank0 parameters and s...

Page 458: ...d Wait States The flash controller is configurable in terms of the number of memory bus cycles it takes to service any read command This allows the CPU execution frequency to be higher than the maximu...

Page 459: ...to four entire flash word width 128 bits in one program operation MSP432 Driver Library API in Table 9 3 can be used to program memory This function can be used to program memory blocks of any size fr...

Page 460: ...in and Information memory space are set to 1 This is followed by initiating a mass erase operation which clears the targeted 128KB in one erase cycle thereby saving time and energy overhead NOTE If IP...

Page 461: ...This ensures that all subsequent reads happen in the targeted mode otherwise a few of the reads to the Bank may continue to be serviced in the old mode MSP432 Driver Library API in Table 9 7 can be u...

Page 462: ...is required following every program operation When pre program verify is enabled flash controller initiates a read to the address to be programed in program verify read mode The flash controller then...

Page 463: ...controller now has a complete 128 bit write word that is used for the program operation NOTE The application can write a single byte to the LSB to start the word composition and a single byte to the M...

Page 464: ...CPU execution of other tasks or put device in LPM0 YES AVPRE 1 or AVPST 1 End of word programming YES A NO Size of the variables w i l l v a r y b e t w e e n immediate and full word p r o g r a m m i...

Page 465: ...e bit wise operations RD_MODE Normal Read WAIT wait states for normal read mode Clear all error flags in FLCTL_CLRIFG register Initiate data write to the desired flash address with updated_new_data Pr...

Page 466: ...WAIT wait states for normal read mode Clear all error flags in FLCTL_CLRIFG register Enable pre and post verify option in FLCTL_PRG_CTLSTAT register Initiate data write to the desired flash address w...

Page 467: ...the CPU and DMA The FLCTL_PRGBRST_DATAx_y registers are used to load the burst data Start address register The start address is configured in the FLCTL_PRGBRST_STARTADDR register must be a 128 bit bo...

Page 468: ...r BURST_STATUS by setting CLR_STAT 1 in FLCTL_PRGBRST_CTLSTAT NO Write data to be programmed into the burst data registers FLCTL_PRGBRST_DATAn_x Setup start address of burst operation in FLCTL_PRGBRST...

Page 469: ...ta Re start burst programming by writing START bit in FLCTL_PRGBRST_CTLSTAT register AUTO_PRE can be disabled since the failing bits have been masked PST_ERR 1 End of word programming NO YES F NO PRGB...

Page 470: ...PRGBRST_CTLSTAT register AUTO_PRE can be disabled since the failing bits have been masked fail_bits 0 NO Clear all error flags in FLCTL_CLRIFG and FLCTL_PRGBRST_CTLSTAT registers YES RD_MODE _STATUS N...

Page 471: ...imum number of erase pulses that is defined by the flash maximum erase pulses parameter in the device data sheet Device Descriptors TLV section The following flash erase modes are supported Sector era...

Page 472: ...below 1 Set Bank 0 in the wait state corresponding to erase verify mode of operation 2 Set Bank 0 in erase verify mode of operation using RD_MODE field of the FLCTL_BANK0_RDCTL register 3 Poll on the...

Page 473: ...capability The interrupt generation logic can be configured to monitor either of the benchmark counters and generate an event when the counter in consideration reaches a particular value 9 3 6 Suppor...

Page 474: ...rently being serviced continues Outstanding flash operations are processed as normal New accesses or operations are processed as normal 9 3 7 2 Hard Reset or POR Reset Class 2 A Hard Reset has the fol...

Page 475: ...n 9 4 17 078h FLCTL_PRGBRST_DATA1_2 Program Burst Data1 Register2 Section 9 4 18 07Ch FLCTL_PRGBRST_DATA1_3 Program Burst Data1 Register3 Section 9 4 19 080h FLCTL_PRGBRST_DATA2_0 Program Burst Data2...

Page 476: ...10Ch FLCTL_ERSVER_TIMCTL Erase Verify Timing Control Register Section 9 4 45 114h FLCTL_PROGRAM_TIMCTL Program Timing Control Register Section 9 4 46 118h FLCTL_ERASE_TIMCTL Erase Timing Control Regis...

Page 477: ...ved Reads return 0h 7 RD_2T R 1h Indicates if Flash is being accessed in 2T mode 0b Flash reads are in 1T mode 1b Flash reads are in 2T mode 6 TRIMSTAT R 0h PSS trim done status 0b PSS trim not comple...

Page 478: ...ffected If this is not followed the device behavior is not deterministic 4 This bit field is writable only when burst status 17 16 of the FLCTL_RDBRST_CTLSTAT shows the Idle state In all other cases t...

Page 479: ...ler FLCTL Table 9 14 FLCTL_BANK0_RDCTL Register Description continued Bit Field Type Reset Description 5 These bits are forced to 0h when the device is in 2T mode of operation 3 0 RD_MODE 1 5 4 RW 0h...

Page 480: ...ffected If this is not followed the device behavior is not deterministic 4 This bit field is writable only when burst status 17 16 of the FLCTL_RDBRST_CTLSTAT shows the Idle state In all other cases t...

Page 481: ...r FLCTL Table 9 15 FLCTL_BANK1_RDCTL Register Description continued Bit Field Type Reset Description 5 These bits are forced to 0h when the device is in 2T mode of operation 3 0 RD_MODE 1 5 4 RW 0h Fl...

Page 482: ...f operation Table 9 16 FLCTL_RDBRST_CTLSTAT Register Description Bit Field Type Reset Description 31 24 Reserved R NA Reserved Reads return 0h 23 CLR_STAT 1 W NA Write 1 to clear status bits 19 16 of...

Page 483: ...0 rw 0 r r r r 1 If the amount of memory available is less than 2MB the upper bits of the START_ADDRESS behave as reserved To know the amount of Flash memory available refer to the device data sheet...

Page 484: ...0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 r r r r 1 If amount of memory available is less than 2MB the upper bits of the BURST_LENGTH behave as reserved To know actual amount of Flash memory available refer to...

Page 485: ...register to 0h before starting a new burst compare operation 2 If amount of memory available is less than 2MB the upper bits of the FAIL_ADDR behave as reserved To know actual amount of Flash memory a...

Page 486: ...on may choose to clear this register to 0h before starting a new burst compare operation If the register is not cleared it increments from the current value each time a new burst is started 2 FAIL_COU...

Page 487: ...A Reserved Reads return 0h 18 BNK_ACT R 0h Reflects which bank is currently undergoing a program operation valid only if bits 17 16 don t show idle 0b Word in Bank0 being programmed 1b Word in Bank1 b...

Page 488: ...21 16 of this register Write 0 has no effect 22 Reserved R NA Reserved Reads return 0h 21 ADDR_ERR R 0h If 1 indicates that Burst Operation was terminated due to attempted program of reserved memory...

Page 489: ...ion 001b 1 word burst of 128 bits starting with address in the FLCTL_PRGBRST_STARTADDR Register 010b 2 128 bits burst write starting with address in the FLCTL_PRGBRST_STARTADDR Register 011b 3 128 bit...

Page 490: ...w 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 r 0 r 0 r 0 r 0 1 Start Address is set as max of 4MB for future enhancement purposes To know actual amount of Flash memory available refer to the device data sheet 2...

Page 491: ...e 9 24 FLCTL_PRGBRST_DATA0_0 Register Description Bit Field Type Reset Description 31 0 DATAIN 1 RW FFFF_FF FFh Program Burst 128 bit Data Word 0 bits 32 x 1 1 down to 32 x for x 0 1 2 3 9 4 13 FLCTL_...

Page 492: ...e 9 26 FLCTL_PRGBRST_DATA0_2 Register Description Bit Field Type Reset Description 31 0 DATAIN 1 RW FFFF_FF FFh Program Burst 128 bit Data Word 0 bits 32 x 1 1 down to 32 x for x 0 1 2 3 9 4 15 FLCTL_...

Page 493: ...e 9 28 FLCTL_PRGBRST_DATA1_0 Register Description Bit Field Type Reset Description 31 0 DATAIN 1 RW FFFF_FF FFh Program Burst 128 bit Data Word 1 bits 32 x 1 1 down to 32 x for x 0 1 2 3 9 4 17 FLCTL_...

Page 494: ...e 9 30 FLCTL_PRGBRST_DATA1_2 Register Description Bit Field Type Reset Description 31 0 DATAIN 1 RW FFFF_FF FFh Program Burst 128 bit Data Word 1 bits 32 x 1 1 down to 32 x for x 0 1 2 3 9 4 19 FLCTL_...

Page 495: ...e 9 32 FLCTL_PRGBRST_DATA2_0 Register Description Bit Field Type Reset Description 31 0 DATAIN 1 RW FFFF_FF FFh Program Burst 128 bit Data Word 2 bits 32 x 1 1 down to 32 x for x 0 1 2 3 9 4 21 FLCTL_...

Page 496: ...e 9 34 FLCTL_PRGBRST_DATA2_2 Register Description Bit Field Type Reset Description 31 0 DATAIN 1 RW FFFF_FF FFh Program Burst 128 bit Data Word 2 bits 32 x 1 1 down to 32 x for x 0 1 2 3 9 4 23 FLCTL_...

Page 497: ...e 9 36 FLCTL_PRGBRST_DATA3_0 Register Description Bit Field Type Reset Description 31 0 DATAIN 1 RW FFFF_FF FFh Program Burst 128 bit Data Word 3 bits 32 x 1 1 down to 32 x for x 0 1 2 3 9 4 25 FLCTL_...

Page 498: ...e 9 38 FLCTL_PRGBRST_DATA3_2 Register Description Bit Field Type Reset Description 31 0 DATAIN 1 RW FFFF_FF FFh Program Burst 128 bit Data Word 3 bits 32 x 1 1 down to 32 x for x 0 1 2 3 9 4 27 FLCTL_...

Page 499: ...4 Writes to the START bit are ignored if the device is in Low Frequency Active and Low Frequency LPM0 modes of operation Table 9 40 FLCTL_ERASE_CTLSTAT Register Description Bit Field Type Reset Descri...

Page 500: ...1 Start Address is set as max of 4MB for future enhancement purposes To know actual amount of Flash memory available refer to the device data sheet 2 This bit field is writable only when status 17 16...

Page 501: ...r r r r r r r r rw 1 rw 1 1 If this Sector falls under a secure memory zone its WEPROT bit is always set to 1 and cannot be overridden to 0 2 This bit field is writable only when status fields of the...

Page 502: ...ns 24 PROT24 1 2 RW 1h If set to 1 protects Sector 24 from program or erase operations 23 PROT23 1 2 RW 1h If set to 1 protects Sector 23 from program or erase operations 22 PROT22 1 2 RW 1h If set to...

Page 503: ...cumentation Feedback Copyright 2015 2019 Texas Instruments Incorporated Flash Controller FLCTL NOTE In case Bank0 of the Main Memory contains less than 32 sectors upper bits behave as reserved Refer t...

Page 504: ...r r r r r r r r rw 1 rw 1 1 If this Sector falls under a secure memory zone its WE bit is always set to 1 and cannot be overridden to 0 2 This bit field is writable only when status fields of the FLCT...

Page 505: ...24 PROT24 1 2 RW 1h If set to 1 protects Sector 24 from program or erase operations 23 PROT23 1 2 RW 1h If set to 1 protects Sector 23 from program or erase operations 22 PROT22 1 2 RW 1h If set to 1...

Page 506: ...mentation Feedback Copyright 2015 2019 Texas Instruments Incorporated Flash Controller FLCTL NOTE In case Bank1 of the Main Memory contains less than 32 sectors upper bits behave as reserved Refer to...

Page 507: ...0 rw 0 rw 0 Table 9 46 FLCTL_BMRK_CTLSTAT Register Description Bit Field Type Reset Description 31 4 Reserved R NA Reserved Reads return 0h 3 CMP_SEL RW 0h Selects which benchmark register should be c...

Page 508: ...41 FLCTL_BMRK_IFETCH Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 COUNT rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1...

Page 509: ...FLCTL_BMRK_DREAD Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 COUNT rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 C...

Page 510: ..._CMP Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 COUNT rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 COUNT rw 0 rw...

Page 511: ...Reads return 0h 9 PRG_ERR R 0h If set to 1 indicates a word composition error in full word write mode possible data loss due to writes crossing over to a new 128bit boundary before full word has been...

Page 512: ...based on the corresponding bit in the FLCTL_IFG 8 BMRK RW 0h If set to 1 enables the Controller to generate an interrupt based on the corresponding bit in the FLCTL_IFG 7 6 Reserved RW 0h Reserved 5 E...

Page 513: ...it Field Type Reset Description 31 10 Reserved R NA Reserved Reads return 0h 9 PRG_ERR W NA Write 1 clears the corresponding interrupt flag bit in the FLCTL_IFG 8 BMRK W NA Write 1 clears the correspo...

Page 514: ...ption Bit Field Type Reset Description 31 10 Reserved R NA Reserved Reads return 0h 9 PRG_ERR W NA Write 1 sets the corresponding interrupt flag bit in the FLCTL_IFG 8 BMRK W NA Write 1 sets the corre...

Page 515: ...r r r r r r r r r r r r r r r r 1 All delays are in terms of clock cycles of a 5 MHz reference clock source Table 9 54 FLCTL_READ_TIMCTL Register Description Bit Field Type Reset Description 31 24 Res...

Page 516: ...ations Figure 9 49 FLCTL_READMARGIN_TIMCTL Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved r r r r r r r r r r r r r r r r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved SETUP r r r...

Page 517: ...20 19 18 17 16 Reserved r r r r r r r r r r r r r r r r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 HOLD ACTIVE SETUP r r r r r r r r r r r r r r r r 1 All delays are in terms of clock cycles of a 5 MHz re...

Page 518: ...51 FLCTL_ERSVER_TIMCTL Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved r r r r r r r r r r r r r r r r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved SETUP r r r r r r r r r r r r r...

Page 519: ...27 26 25 24 23 22 21 20 19 18 17 16 HOLD ACTIVE r r r r r r r r r r r r r r r r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ACTIVE SETUP r r r r r r r r r r r r r r r r 1 All delays are in terms of clock c...

Page 520: ...7 26 25 24 23 22 21 20 19 18 17 16 HOLD ACTIVE r r r r r r r r r r r r r r r r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ACTIVE SETUP r r r r r r r r r r r r r r r r 1 All delays are in terms of clock cyc...

Page 521: ...8 17 16 Reserved r r r r r r r r r r r r r r r r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BOOST_HOLD BOOST_ACTIVE r r r r r r r r r r r r r r r r 1 All delays are in terms of clock cycles of a 5 MHz refe...

Page 522: ...tions Figure 9 55 FLCTL_BURSTPRG_TIMCTL Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved ACTIVE r r r r r r r r r r r r r r r r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ACTIVE Reserved r...

Page 523: ...lash Controller A FLCTL_A Chapter 10 SLAU356I March 2015 Revised June 2019 Flash Controller A FLCTL_A This chapter describes the Flash Controller A module Topic Page 10 1 Introduction 524 10 2 Common...

Page 524: ...the information memory sectors are used by TI and others are available for users Details on information memory are available in the device specific data sheet 10 1 2 Flash Controller Address Mapping...

Page 525: ...ead Flash read operations involve a data value being output by the flash memory 10 2 2 1 Flash Read Timing Control and Wait States The flash controller can configure the number of memory bus cycles to...

Page 526: ...ingle bit up to four entire flash word width 128 bits in one program operation The MSP432 Driver Library API in Table 10 3 can be used to program memory This function can be used to program memory blo...

Page 527: ...emory space are set to 1 This is followed by initiating a mass erase operation which clears the targeted 128KB in one erase cycle thereby saving time and energy overhead NOTE If IP protection is enabl...

Page 528: ...MSP432 Driver Library API in Table 10 7 can be used to configure the read mode Table 10 7 MSP432 Driver Library API for Setting up FLCTL_A Read Modes MSP432 Driver Library API Function FlashCtl_A_setR...

Page 529: ...ler then compares the data received with the value that was intended to be programmed and issues an error if any of the bits that were programed are 1 erased This error is indicated by the AVPST flag...

Page 530: ...a while the intermediate data bits are filled with 1s masked from programming NOTE The application must ensure that the writes in this mode follow the correct sequence LSB initiation and MSB completio...

Page 531: ...xecution of other tasks or put device in LPM0 YES AVPRE 1 or AVPST 1 End of word programming YES A NO Size of the variables w i l l v a r y b e t w e e n immediate and full word p r o g r a m m i n g...

Page 532: ...it wise operations RD_MODE Normal Read WAIT wait states for normal read mode Clear all error flags in FLCTL_CLRIFG register Initiate data write to the desired flash address with updated_new_data Pre v...

Page 533: ...AIT wait states for normal read mode Clear all error flags in FLCTL_CLRIFG register Enable pre and post verify option in FLCTL_PRG_CTLSTAT register Initiate data write to the desired flash address wit...

Page 534: ...direct writes from the CPU and DMA The FLCTL_PRGBRST_DATAx_y registers are used to load the burst data Start address register The start address is configured in the FLCTL_PRGBRST_STARTADDR register m...

Page 535: ...URST_STATUS by setting CLR_STAT 1 in FLCTL_PRGBRST_CTLSTAT NO Write data to be programmed into the burst data registers FLCTL_PRGBRST_DATAn_x Setup start address of burst operation in FLCTL_PRGBRST_ST...

Page 536: ...Re start burst programming by writing START bit in FLCTL_PRGBRST_CTLSTAT register AUTO_PRE can be disabled since the failing bits have been masked PST_ERR 1 End of word programming NO YES F NO PRGB 1...

Page 537: ...GBRST_CTLSTAT register AUTO_PRE can be disabled since the failing bits have been masked fail_bits 0 NO Clear all error flags in FLCTL_CLRIFG and FLCTL_PRGBRST_CTLSTAT registers YES RD_MODE _STATUS Nor...

Page 538: ...of erase pulses that is defined by the flash maximum erase pulses parameter in the device data sheet Device Descriptors TLV section The following flash erase modes are supported Sector erase Mass era...

Page 539: ...ank 0 Sector 0 Pseudo code for this operation follows 1 Set Bank 0 in the wait state corresponding to erase verify mode of operation 2 Set Bank 0 in erase verify mode of operation using RD_MODE field...

Page 540: ...er also implements a compare based interrupt generation capability The interrupt generation logic can be configured to monitor either of the benchmark counters and generate an event when the counter r...

Page 541: ...urrently being serviced continues Outstanding flash operations are processed normally New accesses or operations are processed normally 10 3 7 2 Hard Reset or POR Reset Class 2 A hard reset has the fo...

Page 542: ...FLCTL_PRGBRST_DATA2_2 Program Burst Data2 Register2 Section 10 4 22 08Ch FLCTL_PRGBRST_DATA2_3 Program Burst Data2 Register3 Section 10 4 23 090h FLCTL_PRGBRST_DATA3_0 Program Burst Data3 Register0 S...

Page 543: ...y Bank0 Write Erase Protection Register6 Section 10 4 56 21Ch FLCTL_BANK0_MAIN_WEPROT7 Main Memory Bank0 Write Erase Protection Register7 Section 10 4 57 240h FLCTL_BANK1_MAIN_WEPROT0 Main Memory Bank...

Page 544: ...Reserved Reads return 0h 7 RD_2T R 1h Indicates if Flash is being accessed in 2T mode 0b Flash reads are in 1T mode 1b Flash reads are in 2T mode 6 TRIMSTAT R 0h PSS trim done status 0b PSS trim not c...

Page 545: ...effected If this is not followed the device behavior will not be deterministic 4 This bit field is writable ONLY when burst status 17 16 of the FLCTL_RDBRST_CTLSTAT shows the Idle state In all other c...

Page 546: ...A FLCTL_A Table 10 14 FLCTL_BANK0_RDCTL Register Description continued Bit Field Type Reset Description 5 These bits will be forced to 0h when the device is in 2T mode of operation 3 0 RD_MODE 1 5 4 R...

Page 547: ...ffected If this is not followed the device behavior will not be deterministic 4 This bit field is writable ONLY when burst status 17 16 of the FLCTL_RDBRST_CTLSTAT shows the Idle state In all other ca...

Page 548: ...A FLCTL_A Table 10 15 FLCTL_BANK1_RDCTL Register Description continued Bit Field Type Reset Description 5 These bits will be forced to 0h when the device is in 2T mode of operation 3 0 RD_MODE 1 5 4 R...

Page 549: ...ency LPM0 modes of operation Table 10 16 FLCTL_RDBRST_CTLSTAT Register Description Bit Field Type Reset Description 31 24 Reserved R NA Reserved Reads return 0h 23 CLR_STAT 1 W NA Write 1 to clear sta...

Page 550: ...0 rw 0 r r r r 1 If amount of memory available is less than 2MB the upper bits of the START_ADDRESS will behave as reserved To know actual amount of Flash memory available refer to the device datashe...

Page 551: ...w 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 r r r r 1 If amount of memory available is less than 2MB the upper bits of the BURST_LENGTH will behave as reserved To know actual amount of Flash memory available re...

Page 552: ...egister to 0h before starting a new burst compare operation 2 If amount of memory available is less than 2MB the upper bits of the FAIL_ADDR will behave as reserved To know actual amount of Flash memo...

Page 553: ...Application may choose to clear this register to 0h before starting a new burst compare operation Else it will increment from the current value each time a new burst is started 2 FAIL_COUNT may be as...

Page 554: ...erved R NA Reserved Reads return 0h 18 BNK_ACT R 0h Reflects which bank is currently undergoing a program operation valid only if bits 17 16 don t show idle 0b Word in Bank0 being programmed 1b Word i...

Page 555: ...lear status bits 21 16 of this register Write 0 has no effect 22 Reserved R NA Reserved Reads return 0h 21 ADDR_ERR R 0h If 1 indicates that Burst Operation was terminated due to attempted program of...

Page 556: ...operation 001b 1 word burst of 128 bits starting with address in the FLCTL_PRGBRST_STARTADDR Register 010b 2 128 bits burst write starting with address in the FLCTL_PRGBRST_STARTADDR Register 011b 3 1...

Page 557: ...0 rw 0 rw 0 rw 0 r 0 r 0 r 0 r 0 1 if amount of memory available is less than 2MB the upper bits of the START_ADDRESS will behave as reserved To know actual amount of Flash memory available refer to...

Page 558: ...able 10 24 FLCTL_PRGBRST_DATA0_0 Register Description Bit Field Type Reset Description 31 0 DATAIN 1 RW FFFF_FF FFh Program Burst 128 bit Data Word 0 bits 32 x 1 1 downto 32 x for x 0 1 2 3 10 4 13 FL...

Page 559: ...able 10 26 FLCTL_PRGBRST_DATA0_2 Register Description Bit Field Type Reset Description 31 0 DATAIN 1 RW FFFF_FF FFh Program Burst 128 bit Data Word 0 bits 32 x 1 1 downto 32 x for x 0 1 2 3 10 4 15 FL...

Page 560: ...able 10 28 FLCTL_PRGBRST_DATA1_0 Register Description Bit Field Type Reset Description 31 0 DATAIN 1 RW FFFF_FF FFh Program Burst 128 bit Data Word 1 bits 32 x 1 1 downto 32 x for x 0 1 2 3 10 4 17 FL...

Page 561: ...able 10 30 FLCTL_PRGBRST_DATA1_2 Register Description Bit Field Type Reset Description 31 0 DATAIN 1 RW FFFF_FF FFh Program Burst 128 bit Data Word 1 bits 32 x 1 1 downto 32 x for x 0 1 2 3 10 4 19 FL...

Page 562: ...able 10 32 FLCTL_PRGBRST_DATA2_0 Register Description Bit Field Type Reset Description 31 0 DATAIN 1 RW FFFF_FF FFh Program Burst 128 bit Data Word 2 bits 32 x 1 1 downto 32 x for x 0 1 2 3 10 4 21 FL...

Page 563: ...able 10 34 FLCTL_PRGBRST_DATA2_2 Register Description Bit Field Type Reset Description 31 0 DATAIN 1 RW FFFF_FF FFh Program Burst 128 bit Data Word 2 bits 32 x 1 1 downto 32 x for x 0 1 2 3 10 4 23 FL...

Page 564: ...able 10 36 FLCTL_PRGBRST_DATA3_0 Register Description Bit Field Type Reset Description 31 0 DATAIN 1 RW FFFF_FF FFh Program Burst 128 bit Data Word 3 bits 32 x 1 1 downto 32 x for x 0 1 2 3 10 4 25 FL...

Page 565: ...able 10 38 FLCTL_PRGBRST_DATA3_2 Register Description Bit Field Type Reset Description 31 0 DATAIN 1 RW FFFF_FF FFh Program Burst 128 bit Data Word 3 bits 32 x 1 1 downto 32 x for x 0 1 2 3 10 4 27 FL...

Page 566: ...ils 4 Writes to the START bit will be ignored if the device is in Low Frequency Active and Low Frequency LPM0 modes of operation Table 10 40 FLCTL_ERASE_CTLSTAT Register Description Bit Field Type Res...

Page 567: ...r 1 Start Address is set as max of 4MB for future enhancement purposes To know actual amount of Flash memory available refer to the device datasheet 2 This bit field is writable ONLY when status 17 1...

Page 568: ...its WEPROT bit will always be set to 1 and cannot not be overridden to 0 2 This bit field is writable ONLY when status fields of the FLCTL_PRG_CTLSTAT FLCTL_PRGBRST_CTLSTAT and the FLCTL_ERASE_CTLSTAT...

Page 569: ...se operations 24 PROT24 1 2 RW 1h If set to 1 protects Sector 24 from program or erase operations 23 PROT23 1 2 RW 1h If set to 1 protects Sector 23 from program or erase operations 22 PROT22 1 2 RW 1...

Page 570: ...entation Feedback Copyright 2015 2019 Texas Instruments Incorporated Flash Controller A FLCTL_A NOTE In case Bank0 of the Main Memory contains less than 32 sectors upper bits will behave as reserved R...

Page 571: ...its WEPROT bit will always be set to 1 and cannot not be overridden to 0 2 This bit field is writable ONLY when status fields of the FLCTL_PRG_CTLSTAT FLCTL_PRGBRST_CTLSTAT and the FLCTL_ERASE_CTLSTAT...

Page 572: ...operations 24 PROT24 1 2 RW 1h If set to 1 protects Sector 24 from program or erase operations 23 PROT23 1 2 RW 1h If set to 1 protects Sector 23 from program or erase operations 22 PROT22 1 2 RW 1h...

Page 573: ...tation Feedback Copyright 2015 2019 Texas Instruments Incorporated Flash Controller A FLCTL_A NOTE In case Bank1 of the Main Memory contains less than 32 sectors upper bits will behave as reserved Ref...

Page 574: ...rw 0 rw 0 rw 0 Table 10 46 FLCTL_BMRK_CTLSTAT Register Description Bit Field Type Reset Description 31 4 Reserved R NA Reserved Reads return 0h 3 CMP_SEL RW 0h Selects which benchmark register should...

Page 575: ...e 10 41 FLCTL_BMRK_IFETCH Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 COUNT rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 15 14 13 12 11 10 9 8 7 6 5 4 3...

Page 576: ...42 FLCTL_BMRK_DREAD Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 COUNT rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1...

Page 577: ...BMRK_CMP Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 COUNT rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 COUNT rw 0...

Page 578: ...rved Reads return 0h 9 PRG_ERR R 0h If set to 1 indicates a word composition error in full word write mode possible data loss due to writes crossing over to a new 128bit boundary before full word has...

Page 579: ...upt based on the corresponding bit in the FLCTL_IFG 8 BMRK RW 0h If set to 1 enables the Controller to generate an interrupt based on the corresponding bit in the FLCTL_IFG 7 6 Reserved RW 0h Reserved...

Page 580: ...ion Bit Field Type Reset Description 31 10 Reserved R NA Reserved Reads return 0h 9 PRG_ERR W NA Write 1 clears the corresponding interrupt flag bit in the FLCTL_IFG 8 BMRK W NA Write 1 clears the cor...

Page 581: ...escription Bit Field Type Reset Description 31 10 Reserved R NA Reserved Reads return 0h 9 PRG_ERR W NA Write 1 sets the corresponding interrupt flag bit in the FLCTL_IFG 8 BMRK W NA Write 1 sets the...

Page 582: ...TUP r r r r r r r r r r r r r r r r 1 All delays are in terms of clock cycles of a 5MHz reference clock source Table 10 54 FLCTL_READ_TIMCTL Register Description Bit Field Type Reset Description 31 24...

Page 583: ...perations Figure 10 49 FLCTL_READMARGIN_TIMCTL Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved r r r r r r r r r r r r r r r r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved SETUP r...

Page 584: ...2 21 20 19 18 17 16 Reserved r r r r r r r r r r r r r r r r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 HOLD ACTIVE SETUP r r r r r r r r r r r r r r r r 1 All delays are in terms of clock cycles of a 5MHz...

Page 585: ...e 10 51 FLCTL_ERSVER_TIMCTL Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved r r r r r r r r r r r r r r r r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved SETUP r r r r r r r r r r r...

Page 586: ...9 28 27 26 25 24 23 22 21 20 19 18 17 16 HOLD ACTIVE r r r r r r r r r r r r r r r r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ACTIVE SETUP r r r r r r r r r r r r r r r r 1 All delays are in terms of clo...

Page 587: ...28 27 26 25 24 23 22 21 20 19 18 17 16 HOLD ACTIVE r r r r r r r r r r r r r r r r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ACTIVE SETUP r r r r r r r r r r r r r r r r 1 All delays are in terms of clock...

Page 588: ...19 18 17 16 Reserved r r r r r r r r r r r r r r r r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BOOST_HOLD BOOST_ACTIVE r r r r r r r r r r r r r r r r 1 All delays are in terms of clock cycles of a 5MHz r...

Page 589: ...erations Figure 10 55 FLCTL_BURSTPRG_TIMCTL Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved ACTIVE r r r r r r r r r r r r r r r r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ACTIVE Reserv...

Page 590: ...s 25 PROT25 1 2 RW 1h If set to 1 protects Sector 25 from program or erase operations 24 PROT24 1 2 RW 1h If set to 1 protects Sector 24 from program or erase operations 23 PROT23 1 2 RW 1h If set to...

Page 591: ...TL_A Table 10 62 FLCTL_BANK0_MAIN_WEPROT0 Register Description continued Bit Field Type Reset Description 0 PROT0 1 2 RW 1h If set to 1 protects Sector 0 from program or erase operations NOTE In case...

Page 592: ...operations 24 PROT56 1 2 RW 1h If set to 1 protects Sector 56 from program or erase operations 23 PROT55 1 2 RW 1h If set to 1 protects Sector 55 from program or erase operations 22 PROT54 1 2 RW 1h...

Page 593: ...ight 2015 2019 Texas Instruments Incorporated Flash Controller A FLCTL_A NOTE In case Bank0 of the Main Memory contains less than 64 sectors and greater than 32 sectors upper bits in this register wil...

Page 594: ...operations 24 PROT88 1 2 RW 1h If set to 1 protects Sector 88 from program or erase operations 23 PROT87 1 2 RW 1h If set to 1 protects Sector 87 from program or erase operations 22 PROT86 1 2 RW 1h...

Page 595: ...ight 2015 2019 Texas Instruments Incorporated Flash Controller A FLCTL_A NOTE In case Bank0 of the Main Memory contains less than 96 sectors and greater than 64 sectors upper bits of this register wil...

Page 596: ...operations 24 PROT120 1 2 RW 1h If set to 1 protects Sector 120 from program or erase operations 23 PROT119 1 2 RW 1h If set to 1 protects Sector 119 from program or erase operations 22 PROT118 1 2 R...

Page 597: ...ight 2015 2019 Texas Instruments Incorporated Flash Controller A FLCTL_A NOTE In case Bank0 of the Main Memory contains less than 128 sectors and greater than 96 sectors upper bits of this register wi...

Page 598: ...perations 24 PROT152 1 2 RW 1h If set to 1 protects Sector 152 from program or erase operations 23 PROT151 1 2 RW 1h If set to 1 protects Sector 151 from program or erase operations 22 PROT150 1 2 RW...

Page 599: ...ck Copyright 2015 2019 Texas Instruments Incorporated Flash Controller A FLCTL_A NOTE In case Bank0 of the Main Memory contains less than 160 sectors and greater than 128 sectors upper bits will behav...

Page 600: ...perations 24 PROT184 1 2 RW 1h If set to 1 protects Sector 184 from program or erase operations 23 PROT183 1 2 RW 1h If set to 1 protects Sector 183 from program or erase operations 22 PROT182 1 2 RW...

Page 601: ...pyright 2015 2019 Texas Instruments Incorporated Flash Controller A FLCTL_A NOTE In case Bank0 of the Main Memory contains less than 192 sectors and greater than 160 upper bits of this register will b...

Page 602: ...perations 24 PROT216 1 2 RW 1h If set to 1 protects Sector 216 from program or erase operations 23 PROT215 1 2 RW 1h If set to 1 protects Sector 215 from program or erase operations 22 PROT214 1 2 RW...

Page 603: ...ght 2015 2019 Texas Instruments Incorporated Flash Controller A FLCTL_A NOTE In case Bank0 of the Main Memory contains less than 224 sectors and greater than 192 sectors upper bits of this register wi...

Page 604: ...perations 24 PROT248 1 2 RW 1h If set to 1 protects Sector 248 from program or erase operations 23 PROT247 1 2 RW 1h If set to 1 protects Sector 247 from program or erase operations 22 PROT246 1 2 RW...

Page 605: ...ght 2015 2019 Texas Instruments Incorporated Flash Controller A FLCTL_A NOTE In case Bank0 of the Main Memory contains less than 256 sectors and greater than 224 sectors upper bits of this register wi...

Page 606: ...s 25 PROT25 1 2 RW 1h If set to 1 protects Sector 25 from program or erase operations 24 PROT24 1 2 RW 1h If set to 1 protects Sector 24 from program or erase operations 23 PROT23 1 2 RW 1h If set to...

Page 607: ...TL_A Table 10 70 FLCTL_BANK1_MAIN_WEPROT0 Register Description continued Bit Field Type Reset Description 0 PROT0 1 2 RW 1h If set to 1 protects Sector 0 from program or erase operations NOTE In case...

Page 608: ...operations 24 PROT56 1 2 RW 1h If set to 1 protects Sector 56 from program or erase operations 23 PROT55 1 2 RW 1h If set to 1 protects Sector 55 from program or erase operations 22 PROT54 1 2 RW 1h...

Page 609: ...ight 2015 2019 Texas Instruments Incorporated Flash Controller A FLCTL_A NOTE In case Bank1 of the Main Memory contains less than 64 sectors and greater than 32 sectors upper bits of this register wil...

Page 610: ...operations 24 PROT88 1 2 RW 1h If set to 1 protects Sector 88 from program or erase operations 23 PROT87 1 2 RW 1h If set to 1 protects Sector 87 from program or erase operations 22 PROT86 1 2 RW 1h...

Page 611: ...ight 2015 2019 Texas Instruments Incorporated Flash Controller A FLCTL_A NOTE In case Bank1 of the Main Memory contains less than 96 sectors and greater than 64 sectors upper bits of this register wil...

Page 612: ...operations 24 PROT120 1 2 RW 1h If set to 1 protects Sector 120 from program or erase operations 23 PROT119 1 2 RW 1h If set to 1 protects Sector 119 from program or erase operations 22 PROT118 1 2 R...

Page 613: ...ight 2015 2019 Texas Instruments Incorporated Flash Controller A FLCTL_A NOTE In case Bank1 of the Main Memory contains less than 128 sectors and greater than 96 sectors upper bits of this register wi...

Page 614: ...perations 24 PROT152 1 2 RW 1h If set to 1 protects Sector 152 from program or erase operations 23 PROT151 1 2 RW 1h If set to 1 protects Sector 151 from program or erase operations 22 PROT150 1 2 RW...

Page 615: ...ght 2015 2019 Texas Instruments Incorporated Flash Controller A FLCTL_A NOTE In case Bank1 of the Main Memory contains less than 160 sectors and greater than 128 sectors upper bits of this registers w...

Page 616: ...perations 24 PROT184 1 2 RW 1h If set to 1 protects Sector 184 from program or erase operations 23 PROT183 1 2 RW 1h If set to 1 protects Sector 183 from program or erase operations 22 PROT182 1 2 RW...

Page 617: ...ght 2015 2019 Texas Instruments Incorporated Flash Controller A FLCTL_A NOTE In case Bank1 of the Main Memory contains less than 192 sectors and greater than 160 sectors upper bits of this register wi...

Page 618: ...perations 24 PROT216 1 2 RW 1h If set to 1 protects Sector 216 from program or erase operations 23 PROT215 1 2 RW 1h If set to 1 protects Sector 215 from program or erase operations 22 PROT214 1 2 RW...

Page 619: ...ght 2015 2019 Texas Instruments Incorporated Flash Controller A FLCTL_A NOTE In case Bank1 of the Main Memory contains less than 224 sectors and greater than 192 sectors upper bits of this register wi...

Page 620: ...perations 24 PROT248 1 2 RW 1h If set to 1 protects Sector 248 from program or erase operations 23 PROT247 1 2 RW 1h If set to 1 protects Sector 247 from program or erase operations 22 PROT246 1 2 RW...

Page 621: ...ght 2015 2019 Texas Instruments Incorporated Flash Controller A FLCTL_A NOTE In case Bank1 of the Main Memory contains less than 256 sectors and greater than 224 sectors upper bits of this register wi...

Page 622: ...opyright 2015 2019 Texas Instruments Incorporated DMA Chapter 11 SLAU356I March 2015 Revised June 2019 DMA This chapter describes the features and use of the MSP432P4xx DMA controller module Topic Pag...

Page 623: ...nnels with same priority level are arbitrated using a fixed priority that is determined by the DMA channel number Supports multiple transfer types Memory to memory transfers Memory to peripheral trans...

Page 624: ...ated after the DMA cycle from a channel is complete It is used for generation of the interrupt signal dma_active Signal generated when a channel is serviced by the DMA controller dma_req Input to the...

Page 625: ...cess based on any of the above qualifiers Table 11 1 lists the HPROT signal encoding 1 The controller ties HPROT 0 HIGH to indicate a data access Table 11 1 Protection Signaling HPROT 3 Cacheable HPRO...

Page 626: ...e controller sets dma_active C LOW for at least one hclk cycle before it sets dma_active C 1 or dma_active HIGH 6 For channels that are enabled the controller only permits a single dma_done to be HIGH...

Page 627: ...LOW for at least one hclk cycle T11 If channel C is the highest priority request then the controller asserts dma_active C because of the request at T7 T12 With dma_active C HIGH the controller detects...

Page 628: ...ow many AHB bus transfers occur before it rearbitrates These bits are known as the R_power bits because 2 to the power of R determines the arbitration rate For example if R 4 then the arbitration rate...

Page 629: ...set register see Section 11 3 23 Channel number zero has the highest priority and as the channel number increases the priority of a channel decreases Table 11 5 lists the DMA channel priority levels i...

Page 630: ...g does not significantly increase the latency for high priority channels The following sections describe different cycle types supported in DMA Invalid Cycle Type see Section 11 2 3 4 1 Basic Cycle Ty...

Page 631: ...roller performs 2R transfers for channel C If the number of transfers remaining is zero the flow continues at step 3 2 The controller arbitrates If a higher priority channel is requesting service then...

Page 632: ...In Figure 11 5 Task A 1 The host processor configures the primary data structure for task A 2 The host processor configures the alternate data structure for task This enables the controller to immedi...

Page 633: ...and enters the arbitration process If the channel is enabled for Interrupts then the DMA interrupts the host processor according to the interrupt configuration After task C completes the host process...

Page 634: ...e After this transfer completes the controller starts a DMA cycle using the alternate data structure After this cycle completes the controller performs another four DMA transfers using the primary dat...

Page 635: ...umber of times that the alternate data structure must be configured 13 4 n_minus_1 N 1 Configures the controller to perform N DMA transfers where N is a multiple of four Figure 11 6 shows a memory sca...

Page 636: ...channel and then arbitrates Task C 1 The controller performs task C After it completes the task it generates an auto request for the channel and then arbitrates Primary copy D 1 The controller perfor...

Page 637: ...and those that can be user defined NOTE Peripheral scatter gather mode is almost similar to the memory scatter gather mode with the difference being that during the transfer using the alternate data...

Page 638: ...ization 1 The host processor configures the primary data structure to operate in peripheral scatter gather mode by setting cycle_ctrl to 110b Because a data structure for a single channel consists of...

Page 639: ...After the peripheral issues a new request and it has the highest priority then the process continues with Primary copy D 1 The controller performs four DMA transfers These transfers write the alternat...

Page 640: ...control data structure Figure 11 8 shows the memory that the controller requires for the channel control data structure when it uses all 32 channels and the optional alternate data structure Figure 1...

Page 641: ...of DMA Channels Implemented 9 8 7 6 5 4 3 0 1 A 0x0 0x4 or 0x8 2 A C 0 3 4 A C 1 C 0 5 8 A C 2 C 1 C 0 9 16 A C 3 C 2 C 1 C 0 17 32 A C 4 C 3 C 2 C 1 C 0 Where A Selects one of the channel control da...

Page 642: ...address must be at 0xXXXXXX00 or 0xXXXXXX80 Table 11 10 lists the permitted base address values for the primary data structure depending on the number of channels that the controller contains 1 Where...

Page 643: ...11 11 rc_data_end_ptr Bit Assignments Bit Name Description 31 0 src_data_end_ptr Pointer to the end address of the source data Before the controller can perform a DMA transfer program this memory loca...

Page 644: ...alue that the dst_data_end_ptr memory location contains 29 28 dst_size Destination data size NOTE Set dst_size equal to src_size 27 26 src_inc Set the bits to control the source address increment The...

Page 645: ...he access is non privileged 1 HPROT 1 is HIGH and the access is privileged 17 14 R_power Set these bits to control how many DMA transfers can occur before the controller rearbitrates The possible arbi...

Page 646: ...d the original data structure it performs a DMA cycle using the original data structure The controller continues to perform DMA cycles until it either reads an invalid data structure or the host proce...

Page 647: ...l Trigger register NOTE The DMA transfers are initiated upon rising edge of the peripheral triggers 11 2 6 Interrupts 11 2 6 1 DMA Completion Interrupts The DMA controller outputs both the raw and a m...

Page 648: ...Source Channel Configuration Register RW 0h Section 11 3 6 110h DMA_INT0_SRCFLG Interrupt 0 Source Channel Flag Register RW 0h Section 11 3 7 114h DMA_INT0_CLRFLG Interrupt 0 Source Channel Clear Fla...

Page 649: ...erved r r r r r r r r r r r r r r r r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 NUM_SRC_PER_CHANNEL NUM_DMA_CHANNELS r r r r r r r r r r r r r r r r 1 Refer to appropriate device datasheet for the value i...

Page 650: ...n channel goes active 25 CH25 RW 0h Write 1 triggers DMA_CHANNEL25 Bit is auto cleared when channel goes active 24 CH24 RW 0h Write 1 triggers DMA_CHANNEL24 Bit is auto cleared when channel goes activ...

Page 651: ...l goes active 2 CH2 RW 0h Write 1 triggers DMA_CHANNEL2 Bit is auto cleared when channel goes active 1 CH1 RW 0h Write 1 triggers DMA_CHANNEL1 Bit is auto cleared when channel goes active 0 CH0 RW 0h...

Page 652: ...1 13 DMA_CHn_SRCCFG Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved r r r r r r r r r r r r r r r r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved DMA_SRC r r r r r r r r rw 0 rw 0 r...

Page 653: ...r r rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 1 Enabling DMA_INT1 mapping and selecting a particular channel completion to map to this interrupt will result in the completion being masked from generating INT0 2...

Page 654: ...r r rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 1 Enabling DMA_INT2 mapping and selecting a particular channel completion to map to this interrupt will result in the completion being masked from generating INT0 2...

Page 655: ...mapping and selecting a particular channel completion to map to this interrupt will result in the completion being masked from generating INT0 2 Enabling DMA_INT3 mapping and selecting a particular c...

Page 656: ...R 0h If 1 indicates that Channel 21 was the source of DMA_INT0 20 CH20 R 0h If 1 indicates that Channel 20 was the source of DMA_INT0 19 CH19 R 0h If 1 indicates that Channel 19 was the source of DMA_...

Page 657: ...CH24 W NA Write 1 clears the corresponding flag bit in the DMA_INT0_SRCFLG register Write 0 has no effect 23 CH23 W NA Write 1 clears the corresponding flag bit in the DMA_INT0_SRCFLG register Write...

Page 658: ...in the DMA_INT0_SRCFLG register Write 0 has no effect 5 CH5 W NA Write 1 clears the corresponding flag bit in the DMA_INT0_SRCFLG register Write 0 has no effect 4 CH4 W NA Write 1 clears the correspo...

Page 659: ...nclude the integration test logic 1h Controller includes the integration test logic 27 21 RESERVED R 0h Reserved 20 16 DMACHANS R X Number of available DMA channels minus one 0000b Controller configur...

Page 660: ...SERVED MASTEN w 0 r 0 w 0 Table 11 24 DMA_CFG Register Field Descriptions Bit Field Type Reset Description 31 8 RESERVED R 0h Reserved 7 5 CHPROTCTRL W 0h Sets the AHB Lite protection by controlling t...

Page 661: ...ture The amount of system memory that you must assign to the controller depends on the number of DMA channels and whether you configure it to use the alternate data structure Therefore the base pointe...

Page 662: ...urns the base address of the alternate data structure You cannot read this register when the controller is in the reset state This register removes the necessity for application software to calculate...

Page 663: ...equest status register returns the status of dma_waitonreq You cannot read this register when the controller is in the reset state Figure 11 23 DMA_WAITSTAT Register 31 30 29 28 27 26 25 24 23 22 21 2...

Page 664: ...11 24 DMA_SWREQ Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CHNL_SW_REQ w 0 Table 11 28 DMA_SWREQ Register Field Descriptions Bit Field Type Reset De...

Page 665: ...7 6 5 4 3 2 1 0 SET rw 0 Table 11 29 DMA_USEBURSTSET Register Field Descriptions Bit Field Type Reset Description 31 0 SET RW 0h Returns the useburst status or disables dma_sreq C from generating DMA...

Page 666: ...e 11 26 DMA_USEBURSTCLR Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CLR w 0 Table 11 30 DMA_USEBURSTCLR Register Field Descriptions Bit Field Type Re...

Page 667: ...er 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SET rw 0 Table 11 31 DMA_REQMASKSET Register Field Descriptions Bit Field Type Reset Description 31 0 SET RW 0h...

Page 668: ...QMASKCLR Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CLR w 0 Table 11 32 DMA_REQMASKCLR Register Field Descriptions Bit Field Type Reset Description...

Page 669: ...channels Figure 11 29 DMA_ENASET Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SET rw 0 Table 11 33 DMA_ENASET Register Field Descriptions Bit Field T...

Page 670: ...24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 chnl_enable_clr w 0 Table 11 34 DMA_ENACLR Register Field Descriptions Bit Field Type Reset Description 31 0 CLR W 0h Set the appropria...

Page 671: ...s the channel control data structure status or selects the alternate data structure for the corresponding DMA channel Read as Bit C 0 DMA channel C is using the primary data structure Bit C 1 DMA chan...

Page 672: ...LR W 0h Set the appropriate bit to select the primary data structure for the corresponding DMA channel Write as Bit C 0 No effect Use the DMA_ALTSET Register to select the alternate data structure Bit...

Page 673: ...RIOSET Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SET rw 0 Table 11 37 DMA_PRIOSET Register Field Descriptions Bit Field Type Reset Description 31 0...

Page 674: ...evel Figure 11 34 DMA_PRIOCLR Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CLR w 0 Table 11 38 DMA_PRIOCLR Register Field Descriptions Bit Field Type...

Page 675: ...18 17 16 RESERVED r 0 15 14 13 12 11 10 9 8 RESERVED r 0 7 6 5 4 3 2 1 0 RESERVED ERRCLR r 0 rw 0 Table 11 39 DMA_ERRCLR Register Field Descriptions Bit Field Type Reset Description 31 1 RESERVED R 0h...

Page 676: ...uments Incorporated Digital I O Chapter 12 SLAU356I March 2015 Revised June 2019 Digital I O This chapter describes the operation of the digital I O ports in all devices Topic Page 12 1 Digital I O In...

Page 677: ...t on a rising or falling edge of an input signal All interrupts are fed into an encoded interrupt vector register allowing the application to determine which pin of a port has generated the event Indi...

Page 678: ...t 0 Pin is pulled down Bit 1 Pin is pulled up 12 2 3 Direction Registers PxDIR Each bit in each PxDIR register selects the direction of the corresponding I O pin when it is configured for I O function...

Page 679: ...heral modules is a latched representation of the signal at the device pin While PxSEL1 and PxSEL0 is other than 00 the internal input signal follows the signal at the pin for all connected modules How...

Page 680: ...her interrupt 12 2 7 1 Interrupt Edge Select Registers PxIES Each PxIES bit selects the interrupt edge for the corresponding I O pin Bit 0 Respective PxIFG flag is set on a low to high transition Bit...

Page 681: ...enables wake up from LPM3 LPM4 modes upon digital peripheral input events like UART receive Timer capture and DMA external trigger The PxIE register bits must be set to 1 for the respective I Os to en...

Page 682: ...ote that only the pin conditions are retained All other port configuration register settings such as PxDIR PxREN PxOUT PxIES and PxIE contents are lost Upon exit from LPM3 5 or LPM4 5 modes all periph...

Page 683: ...15 Table 12 3 Digital I O Registers Offset Acronym Register Name Section 0Eh P1IV Port 1 Interrupt Vector Section 12 4 1 1Eh P2IV Port 2 Interrupt Vector Section 12 4 1 2Eh P3IV Port 3 Interrupt Vect...

Page 684: ...nt Selection Section 12 4 9 or PASELC_L 19h P2IES Port 2 Interrupt Edge Select Section 12 4 10 or PAIES_H 1Bh P2IE Port 2 Interrupt Enable Section 12 4 11 or PAIE_H 1Dh P2IFG Port 2 Interrupt Flag Sec...

Page 685: ...nt Selection Section 12 4 9 or PBSELC_L 39h P4IES Port 4 Interrupt Edge Select Section 12 4 10 or PBIES_H 3Bh P4IE Port 4 Interrupt Enable Section 12 4 11 or PBIE_H 3Dh P4IFG Port 4 Interrupt Flag Sec...

Page 686: ...nt Selection Section 12 4 9 or PCSELC_L 59h P6IES Port 6 Interrupt Edge Select Section 12 4 10 or PCIES_H 5Bh P6IE Port 6 Interrupt Enable Section 12 4 11 or PCIE_H 5Dh P6IFG Port 6 Interrupt Flag Sec...

Page 687: ...nt Selection Section 12 4 9 or PDSELC_L 79h P8IES Port 8 Interrupt Edge Select Section 12 4 10 or PDIES_H 7Bh P8IE Port 8 Interrupt Enable Section 12 4 11 or PDIE_H 7Dh P8IFG Port 8 Interrupt Flag Sec...

Page 688: ..._H 85h P10DIR Port 10 Direction Section 12 4 4 or PEDIR_H 87h P10REN Port 10 Resistor Enable Section 12 4 5 or PEREN_H 89h P10DS Port 10 Drive Strength Section 12 4 6 or PEDS_H 8Bh P10SEL0 Port 10 Sel...

Page 689: ...AOUT_L 03h PAOUT_H 04h PADIR Port A Direction 04h PADIR_L 05h PADIR_H 06h PAREN Port A Resistor Enable 06h PAREN_L 07h PAREN_H 08h PADS Port A Drive Strength 08h PADS_L 09h PADS_H 0Ah PASEL0 Port A Se...

Page 690: ...BOUT_L 23h PBOUT_H 24h PBDIR Port B Direction 24h PBDIR_L 25h PBDIR_H 26h PBREN Port B Resistor Enable 26h PBREN_L 27h PBREN_H 28h PBDS Port B Drive Strength 28h PBDS_L 29h PBDS_H 2Ah PBSEL0 Port B Se...

Page 691: ...COUT_L 43h PCOUT_H 44h PCDIR Port C Direction 44h PCDIR_L 45h PCDIR_H 46h PCREN Port C Resistor Enable 46h PCREN_L 47h PCREN_H 48h PCDS Port C Drive Strength 48h PCDS_L 49h PCDS_H 4Ah PCSEL0 Port C Se...

Page 692: ...DOUT_L 63h PDOUT_H 64h PDDIR Port D Direction 64h PDDIR_L 65h PDDIR_H 66h PDREN Port D Resistor Enable 66h PDREN_L 67h PDREN_H 68h PDDS Port D Drive Strength 68h PDDS_L 69h PDDS_H 6Ah PDSEL0 Port D Se...

Page 693: ...EOUT_L 83h PEOUT_H 84h PEDIR Port E Direction 84h PEDIR_L 85h PEDIR_H 86h PEREN Port E Resistor Enable 86h PEREN_L 87h PEREN_H 88h PEDS Port E Drive Strength 88h PEDS_L 89h PEDS_H 8Ah PESEL0 Port E Se...

Page 694: ...Resistor Enable 126h PJREN_L Section 12 4 5 127h PJREN_H Section 12 4 5 128h PJDS Port J Drive Strength 128h PJDS_L Section 12 4 6 129h PJDS_H Section 12 4 6 12Ah PJSEL0 Port J Select 0 12Ah PJSEL0_L...

Page 695: ...eserved R 0h Reserved Reads return 0h 4 0 PxIV R 0h Port x interrupt vector value 00h No interrupt pending 02h Interrupt Source Port x 0 interrupt Interrupt Flag PxIFG 0 Interrupt Priority Highest 04h...

Page 696: ...7 8 9 10 or J Figure 12 3 PxOUT Register 7 6 5 4 3 2 1 0 PxOUT rw rw rw rw rw rw rw rw Table 12 6 PxOUT Register Description Bit Field Type Reset Description 7 0 PxOUT RW Undefine d Port X output Whe...

Page 697: ...0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 Table 12 9 PxDS Register Description Bit Field Type Reset Description 7 0 PxDS RW 0h Port X drive strength selection for high drive strength I Os 0b High drive strengt...

Page 698: ...e function is selected 11b Tertiary module function is selected 12 4 9 PxSELC Register Port X Complement Selection X 1 2 3 4 5 6 7 8 9 10 or J Figure 12 9 PxSELC Register 7 6 5 4 3 2 1 0 PxSELC rw 0 r...

Page 699: ...0 rw 0 Table 12 14 PxIE Register Description Bit Field Type Reset Description 7 0 PxIE RW 0h Port X interrupt enable 0b Corresponding port interrupt disabled 1b Corresponding port interrupt enabled 1...

Page 700: ...PMAP Chapter 13 SLAU356I March 2015 Revised June 2019 Port Mapping Controller PMAP The port mapping controller allows a flexible mapping of digital functions to port pins This chapter describes the p...

Page 701: ...nd attempt to enable write access by writing the correct key is ignored and the registers remain locked A hard reset is required to disable the permanent lock again If it is necessary to reconfigure t...

Page 702: ...PM_TA1CCR2A TimerA1 CCR2 capture input CCI2A TimerA1 CCR2 compare output Out2 PM_TB0CLK TimerB0 clock input DVSS PM_TB0OUTH TimerB0 outputs high impedance DVSS PM_TB0CCR0A TimerB0 CCR0 capture input...

Page 703: ...ncorporated Port Mapping Controller PMAP Table 13 1 Examples for Port Mapping Mnemonics and Functions continued PxMAPy Mnemonic Input Pin Function With PxSEL y 1 and PxDIR y 0 Output Pin Function With...

Page 704: ...Section 13 3 10 0Eh P1MAP67 Port mapping register P1 6 and P1 7 Read write Half word X Section 13 3 10 10h P2MAP01 Port mapping register P2 0 and P2 1 Read write Half word X Section 13 3 10 12h P2MAP...

Page 705: ...ection 3Ch P7MAP45 Port mapping register P7 4 and P7 5 Read write Half word X Section 13 3 10 3Eh P7MAP67 Port mapping register P7 6 and P7 7 Read write Half word X Section 13 3 10 NOTE This is a 16 b...

Page 706: ...Reserved PMAPRECFG PMAPLOCKED r 0 r 0 r 0 r 0 r 0 r 0 rw 0 r 1 Table 13 4 PMAPCTL Register Description Bit Field Type Reset Description 15 2 Reserved R 0h Reserved Always reads as 0 1 PMAPRECFG RW 0h...

Page 707: ...o P3MAP7 Register 7 6 5 4 3 2 1 0 PMAPx rw 1 rw 1 rw 1 rw 1 rw 1 rw 1 rw 1 rw 1 Table 13 7 P3MAP0 to P3MAP7 Register Description Bit Field Type Reset Description 7 0 PMAPx RW X Selects secondary port...

Page 708: ...ice specific data sheet 13 3 9 P7MAP0 to P7MAP7 Register offset 38h to 3Fh reset X Port Mapping Register P7 x x 0 to 7 1 If not all bits are required to decode all provided functions the unused bits a...

Page 709: ...rated Capacitive Touch IO CAPTIO Chapter 14 SLAU356I March 2015 Revised June 2019 Capacitive Touch IO CAPTIO This chapter describes the functionality of the Capacitive Touch IOs and related control To...

Page 710: ...truments Incorporated Capacitive Touch IO CAPTIO 14 1 Capacitive Touch IO Introduction The Capacitive Touch IO module allows implementation of a simple capacitive touch sense application The module us...

Page 711: ...f the Capacitive Touch IO module Figure 14 2 Capacitive Touch IO Block Diagram 14 2 Capacitive Touch IO Operation Enable the Capacitive Touch IO functionality with CAPTIOEN 1 and select a port pin usi...

Page 712: ...neric register ANYREG the suffix _L ANYREG_L refers to the lower byte of the register bits 0 through 7 The suffix _H ANYREG_H refers to the upper byte of the register bits 8 through 15 Table 14 1 CapT...

Page 713: ...isabled 0b Curent state 0 or Capacitive Touch IO is disabled 1b Current state 1 8 CAPTIOEN RW 0h Capacitive Touch IO enable 0b All Capacitive Touch IOs are disabled Signal towards timers is 0 1b Selec...

Page 714: ...LAU356I March 2015 Revised June 2019 CRC32 Module The 16 bit or 32 bit cyclic redundancy check CRC32 module provides a signature for a given data sequence This chapter describes the operation and use...

Page 715: ...x10 x8 x7 x5 x4 x2 x 1 Figure 15 2 LFSR Implementation of CRC32 ISO3309 as Defined in Standard Bit0 is MSB Identical input data sequences result in identical signatures when the CRC is initialized wi...

Page 716: ...identical behavior as the LFSR approach After a set of 8 16 or 32 bits is provided to the CRC32 module by writing to the CRC16DI or CRC32DI registers a calculation for the whole set of input bits is p...

Page 717: ...IRES_LO CRC32 Initialization and Result Low Section 15 3 0 3 000Ah CRC32INIRES_HI CRC32 Initialization and Result High Section 15 3 0 4 000Ch CRC32RESR_LO CRC32 Result Reverse Low Section 15 3 0 5 000...

Page 718: ...15 3 CRC32DI Register 15 14 13 12 11 10 9 8 CRC32DI rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 7 6 5 4 3 2 1 0 CRC32DI rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 Table 15 2 CRC32DI Register Description Bit...

Page 719: ...4 CRC32DIRB Register 15 14 13 12 11 10 9 8 CRC32DIRB rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 7 6 5 4 3 2 1 0 CRC32DIRB rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 Table 15 3 CRC32DIRB Register Description...

Page 720: ...rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 7 6 5 4 3 2 1 0 CRC32INIRES_LO rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 1 This register is updated with the final signature value one cycle after the last data input...

Page 721: ...w 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 7 6 5 4 3 2 1 0 CRC32INIRES_HI rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 1 This register is updated with the final signature value one cycle after the last data input v...

Page 722: ...with the final signature value one cycle after the last data input value is written to the CRC32DI or CRC32DIRB registers Application should wait for this one cycle delay before reading the result Tab...

Page 723: ...with the final signature value one cycle after the last data input value is written to the CRC32DI or CRC32DIRB registers Application should wait for this one cycle delay before reading the result Tab...

Page 724: ...r is used in CRC16 signature calculations Figure 15 9 CRC16DI Register 15 14 13 12 11 10 9 8 CRC16DI rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 7 6 5 4 3 2 1 0 CRC16DI rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0...

Page 725: ...15 10 CRC16DIRB Register 15 14 13 12 11 10 9 8 CRC16DIRB rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 7 6 5 4 3 2 1 0 CRC16DIRB rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 Table 15 9 CRC16DIRB Register Descrip...

Page 726: ...rw 1 rw 1 rw 1 rw 1 rw 1 rw 1 rw 1 rw 1 1 This register is updated with the final signature value one cycle after the last data input value is written to the CRC32DI or CRC32DIRB registers Application...

Page 727: ...6RESR rw 1 rw 1 rw 1 rw 1 rw 1 rw 1 rw 1 rw 1 1 This register is updated with the final signature value one cycle after the last data input value is written to the CRC32DI or CRC32DIRB registers Appli...

Page 728: ...h 2015 Revised June 2019 AES256 Accelerator The AES256 accelerator module performs Advanced Encryption Standard AES encryption or decryption in hardware It supports key lengths of 128 bits 192 bits an...

Page 729: ...ing to the advanced encryption standard AES FIPS PUB 197 in hardware The AES accelerator features are AES encryption 128 bit in 168 cycles 192 bit in 204 cycles 256 bit in 234 cycles AES decryption 12...

Page 730: ...ecryption is performed 168 01 AES192 with last roundkey decryption is performed 206 10 AES256 with last roundkey decryption is performed 234 Table 16 1 lists the execution time of the different modes...

Page 731: ...for AESRDYIE AESOPx and AESKLx 16 2 1 Load the Key 128 Bit 192 Bit or 256 Bit Keylength The key can be loaded by writing to the AESAKEY register or by setting AESKEYWR Depending on the selected keyle...

Page 732: ...riting the last byte or half word of the state using AESAXIN does not start encryption or decryption 16 2 3 Read the Data 128 Bit State The state can be read if AESBUSY 0 using 16 byte reads or 8 half...

Page 733: ...as described in Section 16 2 1 3 Load the state data as described in Section 16 2 2 After the data is loaded the AES module starts the encryption 4 After the encryption is ready the result can be read...

Page 734: ...dkey is already generated and will be loaded in step 2 Changing the AESOPx bits clears the AESKEYWR flag and a new key must be loaded in step 2 2 Load the key according to Section 16 2 1 3 Load the st...

Page 735: ...the key as described in Section 16 2 1 The generation of the first round key required for decryption is started immediately 3 While the AES module is performing the key generation the AESBUSY bit is 1...

Page 736: ...with AESCMEN 1 AES trigger 0 is triggered eight times for DMA half word access to read out AESADOUT and then AES trigger 1 is triggered eight times to fill the next data into AESADIN Table 16 2 shows...

Page 737: ...ding the state through the DMA For AESCMEN 0 no DMA triggers are generated The following sections explains the configuration of the AES module for automatic cipher mode execution using DMA It is assum...

Page 738: ...1 1 1 ECB Encryption Figure 16 6 ECB Encryption To implement the ECB encryption without CPU interaction two DMA channels are needed Static DMA priorities must be enabled Table 16 3 AES and DMA Configu...

Page 739: ...ad plaintext from AESADOUT Write ciphertext to AESADIN which also triggers the next decryption The following pseudo code snippet shows the implementation of the ECB decryption in software ECB_Decrypti...

Page 740: ...bytes of the plaintext into AESAXDIN see Figure 16 8 Figure 16 8 CBC Encryption Table 16 5 AES and DMA Configuration for CBC Encryption AES CMEN AES CMx AES OPx DMA_A Triggered by AES trigger 0 DMA_B...

Page 741: ...1 or 11 Write the previous ciphertext block to AESAXIN Read plaintext from AESADOUT Write next plaintext to AESADIN which also triggers the next decryption The following pseudo code snippet shows the...

Page 742: ...ggered by AES trigger 1 DMA_C Triggered by AES trigger 2 1 10 00 Write the plaintext of the current block to AESAXIN Read ciphertext from AESADOUT Write the plaintext of the current block to AESAXDIN...

Page 743: ...2 1 10 01 or 11 1 Write the ciphertext of the current block to AESAXIN Read plaintext from AESADOUT Write the ciphertext of the current block to AESAXDIN which also triggers the next encryption The f...

Page 744: ...FB Encryption AES CMEN AES CMx AES OPx DMA_A Triggered by AES trigger 0 DMA_B Triggered by AES trigger 1 1 11 00 Write the plaintext of the current block to AESAXIN Read the ciphertext from AESADOUT w...

Page 745: ...01 or 11 1 Write the ciphertext of the current block to AESAXIN Read the plaintext from AESADOUT Write the ciphertext of the current block to AESADIN which also triggers the next encryption The follow...

Page 746: ...r control register 0 Section 16 3 1 02h AESACTL1 AES accelerator control register 1 Section 16 3 2 04h AESASTAT AES accelerator status register Section 16 3 3 06h AESAKEY AES accelerator key register...

Page 747: ...0h AES error flag AESAKEY or AESADIN were written while an AES operation was in progress The bit must be cleared by software 0b No error 1b Error occurred 10 9 Reserved R 0h Reserved 8 AESRDYIFG RW 0...

Page 748: ...r Description continued Bit Field Type Reset Description 1 0 AESOPx RW 0h AES operation The AESOPx bits are not reset by AESSWRST 1 Writes are ignored when AESCMEN 1 and AESBLKCNTx 0 00b Encryption 01...

Page 749: ...0 r 0 7 6 5 4 3 2 1 0 AESBLKCNTx rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 Writes are ignored when AESCMEN 1 and AESBLKCNTx 0 Table 16 13 AESACTL1 Register Description Bit Field Type Reset Description 1...

Page 750: ...TRD R 0h All 16 bytes read from AESADOUT AESDOUTRD is reset by PUC AESSWRST an error condition changing AESOPx changing AESKLx when the AES accelerator is busy and when the output data is read again 0...

Page 751: ...x w 0 w 0 w 0 w 0 w 0 w 0 w 0 w 0 Table 16 15 AESAKEY Register Description Bit Field Type Reset Description 15 8 AESKEY1x W 0h AES key byte n 1 when AESAKEY is written as half word Do not use these bi...

Page 752: ...0 w 0 w 0 w 0 7 6 5 4 3 2 1 0 AESDIN0x w 0 w 0 w 0 w 0 w 0 w 0 w 0 w 0 Table 16 16 AESADIN Register Description Bit Field Type Reset Description 15 8 AESDIN1x W 0h AES data in byte n 1 when AESADIN is...

Page 753: ...UT1x r 0 r 0 r 0 r 0 r 0 r 0 r 0 r 0 7 6 5 4 3 2 1 0 AESDOUT0x r 0 r 0 r 0 r 0 r 0 r 0 r 0 r 0 Table 16 17 AESADOUT Register Description Bit Field Type Reset Description 15 8 AESDOUT1x R 0h AES data o...

Page 754: ...0 w 0 w 0 w 0 7 6 5 4 3 2 1 0 AESXDIN0x w 0 w 0 w 0 w 0 w 0 w 0 w 0 w 0 Table 16 18 AESAXDIN Register Description Bit Field Type Reset Description 15 8 AESXDIN1x W 0h AES data in byte n 1 when AESAXD...

Page 755: ...0 w 0 w 0 w 0 w 0 w 0 7 6 5 4 3 2 1 0 AESXIN0x w 0 w 0 w 0 w 0 w 0 w 0 w 0 w 0 Table 16 19 AESAXIN Register Description Bit Field Type Reset Description 15 8 AESXIN1x W 0h AES data in byte n 1 when A...

Page 756: ...SLAU356I March 2015 Revised June 2019 Watchdog Timer WDT_A The watchdog timer is a 32 bit timer that can be used as a watchdog or as an interval timer This chapter describes the watchdog timer and its...

Page 757: ...If the selected time interval expires a system reset is generated If the watchdog function is not needed in an application the module can be configured as an interval timer and can generate interrupts...

Page 758: ...Asyn Int Flag Pulse Generator VLOCLK Clock Request Logic SMCLK request ACLK request VLOCLK request 10 11 Q9 Q13 Q15 Q19 Q23 Q27 Q31 BCLK 11 10 01 00 11 10 01 00 0 1 16 bit Counter CLK BCLK request WD...

Page 759: ...sourced from SMCLK ACLK VLOCLK and BCLK The clock source is selected with the WDTSSEL bits The timer interval is selected with the WDTIS bits This counter is automatically reset on a Soft Reset or hi...

Page 760: ...reset was caused by a different source 17 2 5 Clock Sources of the WDT_A The WDT_A provides multiple options for the clock that can be used to source the counter either in watchdog or in interval time...

Page 761: ...nly in interval timer mode This is because there is no execution activity to handle the watchdog On the other hand if the WDT_A is configured as an interval timer the interval timer event can be used...

Page 762: ...ule registers and their address offsets The base address can be found in the device specific data sheet Table 17 2 WDT_A Registers Offset Acronym Register Name Section 0Ch WDTCTL Watchdog Timer Contro...

Page 763: ...Must be written as 05Ah or the WDT generates a reset 7 WDTHOLD RW 0h Watchdog timer hold This bit stops the watchdog timer Setting WDTHOLD 1 when the WDT is not in use conserves power 0b Watchdog tim...

Page 764: ...Instruments Incorporated Timer32 Chapter 18 SLAU356I March 2015 Revised June 2019 Timer32 This chapter describes the features and functionality of Timer32 Topic Page 18 1 Introduction 765 18 2 Functi...

Page 765: ...ical The timer is loaded by writing to the load register and if enabled counts down to zero When a counter is already running writing to the load register causes the counter to immediately restart at...

Page 766: ...register is written to A register holds the value until the interrupt is cleared The most significant carry bit of the counter detects the counter reaching zero The interrupts can be masked by writing...

Page 767: ...1 Timer 1 Raw Interrupt Status Register R 0h Section 18 5 5 14h T32MIS1 Timer 1 Interrupt Status Register R 0h Section 18 5 6 18h T32BGLOAD1 Timer 1 Background Load Register RW 0h Section 18 5 7 20h T...

Page 768: ...mediately affected If values are written to both the T32LOAD1 and T32BGLOAD1 registers before an enabled rising edge on TIMCLK the following occurs On the next enabled TIMCLK edge the value written to...

Page 769: ...LUE1 Register offset 04h reset FFFFFFFFh This register contains Timer 1 Current Value Figure 18 3 T32VALUE1 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1...

Page 770: ...Description Bit Field Type Reset Description 31 8 Reserved R 0h Reserved 7 ENABLE RW 0h Enable bit 0b Timer disabled 1b Timer enabled 6 MODE RW 0h Mode bit 0b Timer is in free running mode 1b Timer is...

Page 771: ...LR1 Register offset 0Ch reset undefined Timer 1 Interrupt Clear Register Figure 18 5 T32INTCLR1 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 INTCLR w...

Page 772: ...counter This value is combined by a logical AND with the timer interrupt enable bit from the Timer Control Register to create the masked interrupt which is passed to the interrupt output pin Figure 1...

Page 773: ...e counter This value is the logical AND of the raw interrupt status with the timer interrupt enable bit from the Timer Control Register This is the same value that is passed to the interrupt output pi...

Page 774: ...and the current count reaches zero This register provides an alternative method of accessing the T32LOAD1 Register The difference is that writes to T32BGLOAD1 do not cause the counter to immediately r...

Page 775: ...mediately affected If values are written to both the T32LOAD2 and T32BGLOAD2 registers before an enabled rising edge on TIMCLK the following occurs On the next enabled TIMCLK edge the value written to...

Page 776: ...UE2 Register offset 24h reset FFFFFFFFh This register contains Timer 2 Current Value Figure 18 10 T32VALUE2 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1...

Page 777: ...r Description Bit Field Type Reset Description 31 8 Reserved R 0h Reserved 7 ENABLE RW 0h Enable bit 0b Timer disabled 1b Timer enabled 6 MODE RW 0h Mode bit 0b Timer is in free running mode 1b Timer...

Page 778: ...LR2 Register offset 2Ch reset undefined Timer 2 Interrupt Clear Register Figure 18 12 T32INTCLR2 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 INTCLR w...

Page 779: ...counter This value is combined by a logical AND with the timer interrupt enable bit from the Timer Control Register to create the masked interrupt which is passed to the interrupt output pin Figure 18...

Page 780: ...counter This value is the logical AND of the raw interrupt status with the timer interrupt enable bit from the Timer Control Register This is the same value that is passed to the interrupt output pin...

Page 781: ...and the current count reaches zero This register provides an alternative method of accessing the T32LOAD2 Register The difference is that writes to T32BGLOAD2 do not cause the counter to immediately r...

Page 782: ...2015 Revised June 2019 Timer_A Timer_A is a 16 bit timer counter with multiple capture compare registers There can be multiple Timer_A modules on a given device see the device specific data sheet This...

Page 783: ...rable clock source Up to seven configurable capture compare registers Configurable outputs with pulse width modulation PWM capability Asynchronous input and output latching The block diagram of Timer_...

Page 784: ...mer Clock EQU0 Timer Clock Timer Clock TAxCCR6 SCCI Y A EN CCR1 POR TACLR CCR0 Timer Block 00 01 10 11 Set TAxCCR6 CCIFG CAP 1 0 1 0 CCR2 CCR3 ACLK SMCLK TAxCLK INCLK IDEX Divider 1 8 CCR4 CCR5 2 2 3...

Page 785: ...Clock Source Select and Divider The timer clock can be sourced from ACLK SMCLK or externally from TAxCLK or INCLK The clock source is selected with the TASSEL bits The selected clock source may be pa...

Page 786: ...counts The timer repeatedly counts up to the value of compare register TAxCCR0 which defines the period see Figure 19 2 The number of timer counts in the period is TAxCCR0 1 When the timer value equa...

Page 787: ...TAIFG interrupt flag is set when the timer counts from 0FFFFh to zero Figure 19 5 shows the flag set cycle Figure 19 5 Continuous Mode Flag Setting 19 2 3 3 Use of Continuous Mode The continuous mode...

Page 788: ...the same direction it was counting before it was stopped If this is not desired the TACLR bit must be set to clear the direction The TACLR bit also clears the TAxR value and the timer clock divider I...

Page 789: ...ode 19 2 4 Capture Compare Blocks Up to seven identical capture compare blocks TAxCCRn where n 0 to 7 are present in Timer_A Any of the blocks may be used to capture the timer data or to generate time...

Page 790: ...2015 2019 Texas Instruments Incorporated Timer_A Figure 19 10 Capture Signal SCS 1 NOTE Changing Capture Inputs Changing capture inputs while in capture mode may cause unintended capture events To av...

Page 791: ...odes that generate signals based on the EQU0 and EQUn signals 19 2 5 1 Output Modes The output modes are defined by the OUTMOD bits see Table 19 2 The OUTn signal is changed with the rising edge of th...

Page 792: ...nts Timer_A Operation www ti com 792 SLAU356I March 2015 Revised June 2019 Submit Documentation Feedback Copyright 2015 2019 Texas Instruments Incorporated Timer_A 19 2 5 1 1 Output Example Timer in U...

Page 793: ...0 www ti com Timer_A Operation 793 SLAU356I March 2015 Revised June 2019 Submit Documentation Feedback Copyright 2015 2019 Texas Instruments Incorporated Timer_A 19 2 5 1 2 Output Example Timer in Con...

Page 794: ...put Example Timer in Up Down Mode The OUTn signal changes when the timer equals TAxCCRn in either count direction and when the timer equals TAxCCR0 depending on the output mode Figure 19 14 shows an e...

Page 795: ...TAIFG flags are prioritized and combined to source a single interrupt vector The interrupt vector register TAxIV is used to determine which flag requested an interrupt The highest priority enabled int...

Page 796: ...xCTL Timer_Ax Control Section 19 3 1 02h to 0Eh TAxCCTL0 to TAxCCTL6 Timer_Ax Capture Compare Control 0 to Timer_Ax Capture Compare Control 6 Section 19 3 3 10h TAxR Timer_Ax Counter Section 19 3 2 12...

Page 797: ...D RW 0h Input divider These bits along with the TAIDEX bits select the divider for the input clock 00b 1 01b 2 10b 4 11b 8 5 4 MC RW 0h Mode control Setting MCx 00h when Timer_A is not in use conserve...

Page 798: ...imer_A 19 3 2 TAxR Register Timer_Ax Counter Register Figure 19 16 TAxR Register 15 14 13 12 11 10 9 8 TAxR rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 7 6 5 4 3 2 1 0 TAxR rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 r...

Page 799: ...a sheet for specific signal connections 00b CCIxA 01b CCIxB 10b GND 11b VCC 11 SCS RW 0h Synchronize capture source This bit is used to synchronize the capture input signal with the timer clock 0b Asy...

Page 800: ..._A Table 19 6 TAxCCTL0 to TAxCCTL6 Register Description continued Bit Field Type Reset Description 1 COV RW 0h Capture overflow This bit indicates a capture overflow occurred COV must be reset with so...

Page 801: ...to the TAxCCRn register when a capture is performed 19 3 5 TAxIV Register Timer_Ax Interrupt Vector Register Figure 19 19 TAxIV Register 15 14 13 12 11 10 9 8 TAIV r0 r0 r0 r0 r0 r0 r0 r0 7 6 5 4 3 2...

Page 802: ...r divider logic Figure 19 20 TAxEX0 Register 15 14 13 12 11 10 9 8 Reserved r0 r0 r0 r0 r0 r0 r0 r0 7 6 5 4 3 2 1 0 Reserved TAIDEX 1 r0 r0 r0 r0 r0 rw 0 rw 0 rw 0 Table 19 9 TAxEX0 Register Descripti...

Page 803: ...Real Time Clock RTC_C The Real Time Clock RTC_C module provides clock counters with calendar mode a flexible programmable alarm offset calibration and a provision for temperature compensation The RTC_...

Page 804: ...rs day of week day of month month and year including leap year correction Protection for real time clock registers Interrupt capability Selectable BCD or binary format Programmable alarms Real time cl...

Page 805: ...00 011 010 001 000 3 RT0IP RTCHOLD Keepout Logic Set_RTCRDYIFG Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 111 hour changed midnight noon RTCHOUR RTCMIN RTCSEC 110 101 100 011 010 001 000 111 BCLK RTCOCALS RTCOCAL EN Cal...

Page 806: ...Each alarm register contains an alarm enable AE bit that can be used to enable the respective alarm register By setting AE bits of the various alarm registers a variety of alarm events can be generat...

Page 807: ...See tables in Section 20 3 for details on registers covered under the protection scheme RTCCTL0_H register implements key protection and controls lock or unlock state of the module When this register...

Page 808: ...ed after servicing the initial interrupt In addition all flags can be cleared by software The user programmable alarm event sources the real time clock interrupt RTCAIFG Setting RTCAIE enables the int...

Page 809: ...d RTCHOLD 0 or when RTCOCALx bits are zero RTCOCAL should only be written when RTCHOLD 1 Writing RTCOCAL resets temperature compensation to zero In RTC the offset error calibration takes place over a...

Page 810: ...maximum frequency error that can be corrected to account for both offset error and temperature variation is 240ppm This means the sign addition of offset error value and temperature compensation valu...

Page 811: ...perform temperature measurement once every few seconds or once every minute or once in several minutes Writing to the RTCTCMP register for temperature compensation is effective once per one minute Thi...

Page 812: ...interrupts can be serviced as usual The detailed flow is as follows 1 Set all I Os to general purpose I Os and configure them as needed Optionally configure input interrupt pins for wakeup Configure...

Page 813: ...High Read write n a not retained Section 20 3 2 02h RTCCTL13 Real Time Clock Control 1 3 Read write yes high byte retained Section 20 3 3 02h RTCCTL1 Real Time Clock Control 1 Read write yes not reta...

Page 814: ...3 16 or RTCDATE_H 16h RTCYEAR Real Time Clock Year 1 Read write yes retained Section 20 3 18 18h RTCAMINHR Real Time Clock Minutes Hour Alarm Read write no retained 18h RTCAMIN Real Time Clock Minutes...

Page 815: ...ime event interrupt enable 0b Interrupt not enabled 1b Interrupt enabled LPM3 LPM3 5 wake up enabled 5 RTCAIE RW 0h Real time clock alarm interrupt enable 0b Interrupt not enabled 1b Interrupt enabled...

Page 816: ...Real Time Clock Control 0 High Register Figure 20 4 RTCCTL0_H Register 7 6 5 4 3 2 1 0 RTCKEY rw 1 rw 0 rw 0 rw 1 rw 0 rw 1 rw 1 rw 0 Table 20 3 RTCCTL0_H Register Description Bit Field Type Reset Des...

Page 817: ...eal time clock BCD select Selects BCD counting for real time clock 0b Binary hexadecimal code selected 1b Binary coded decimal BCD code selected 6 RTCHOLD RW 1h Real time clock hold 0b Real time clock...

Page 818: ...e LOCKBKUP bit is 0 Figure 20 6 RTCCTL3 Register 7 6 5 4 3 2 1 0 Reserved RTCCALFx 1 r0 r0 r0 r0 r0 r0 rw 0 rw 0 Table 20 5 RTCCTL3 Register Description Bit Field Type Reset Description 7 2 Reserved R...

Page 819: ...3 2 1 0 RTCOCALx 1 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 Table 20 6 RTCOCAL Register Description Bit Field Type Reset Description 15 RTCOCALS RW 0h Real time clock offset error calibration sign This...

Page 820: ...ion sign This bit decides the sign of temperature compensation 1 0b Down calibration Frequency adjusted down 1b Up calibration Frequency adjusted up 14 RTCTCRDY R 1h Real time clock temperature compen...

Page 821: ...rw rw Table 20 8 RTCSEC Register Description Bit Field Type Reset Description 7 6 0 R 0h Always 0 5 0 Seconds RW undefined Seconds 0 to 59 20 3 8 RTCSEC Register BCD Format Real Time Clock Seconds Re...

Page 822: ...rw rw Table 20 10 RTCMIN Register Description Bit Field Type Reset Description 7 6 0 R 0h Always 0 5 0 Minutes RW undefined Minutes 0 to 59 20 3 10 RTCMIN Register BCD Format Real Time Clock Minutes R...

Page 823: ...rw rw rw rw Table 20 12 RTCHOUR Register Description Bit Field Type Reset Description 7 5 0 R 0h Always 0 4 0 Hours RW undefined Hours 0 to 23 20 3 12 RTCHOUR Register BCD Format Real Time Clock Hours...

Page 824: ...lock Day of Month Register Hexadecimal Format Figure 20 16 RTCDAY Register 7 6 5 4 3 2 1 0 0 Day of month r 0 r 0 r 0 rw rw rw rw rw Table 20 15 RTCDAY Register Description Bit Field Type Reset Descri...

Page 825: ...0 rw rw rw rw Table 20 17 RTCMON Register Description Bit Field Type Reset Description 7 4 0 R 0h Always 0 3 0 Month RW undefined Month 1 to 12 20 3 17 RTCMON Register BCD Format Real Time Clock Month...

Page 826: ...h byte RW undefined Year high byte Valid values for Year are 0 to 4095 7 0 Year low byte RW undefined Year low byte Valid values for Year are 0 to 4095 20 3 19 RTCYEAR Register BCD Format Real Time Cl...

Page 827: ...CAMIN Register Description Bit Field Type Reset Description 7 AE RW undefined Alarm enable 6 0 R 0h Always 0 5 0 Minutes RW undefined Minutes 0 to 59 20 3 21 RTCAMIN Register BCD Format Real Time Cloc...

Page 828: ...R Register Description Bit Field Type Reset Description 7 AE RW undefined Alarm enable 6 5 0 R 0h Always 0 4 0 Hours RW undefined Hours 0 to 23 20 3 23 RTCAHOUR Register BCD Format Real Time Clock Hou...

Page 829: ...of Month Alarm Register Hexadecimal Format Figure 20 27 RTCADAY Register 7 6 5 4 3 2 1 0 AE 0 Day of month rw r 0 r 0 rw rw rw rw rw Table 20 26 RTCADAY Register Description Bit Field Type Reset Descr...

Page 830: ...eserved r0 r0 r0 r0 r0 r0 r0 r0 7 6 5 4 3 2 1 0 Reserved RT0IP 1 RT0PSIE RT0PSIFG r0 r0 r0 rw 0 rw 0 rw 0 rw 0 rw 0 Table 20 28 RTCPS0CTL Register Description Bit Field Type Reset Description 15 5 Res...

Page 831: ...served r0 r0 r0 r0 r0 r0 r0 r0 7 6 5 4 3 2 1 0 Reserved RT1IPx 1 RT1PSIE RT1PSIFG r0 r0 r0 rw 0 rw 0 rw 0 rw 0 rw 0 Table 20 29 RTCPS1CTL Register Description Bit Field Type Reset Description 15 5 Res...

Page 832: ...PS0 Register 7 6 5 4 3 2 1 0 RT0PS rw rw rw rw rw rw rw rw Table 20 30 RTCPS0 Register Description Bit Field Type Reset Description 7 0 RT0PS RW undefined Prescale timer 0 counter value 20 3 30 RTCPS1...

Page 833: ...Register Description Bit Field Type Reset Description 15 0 RTCIVx R 0h Real time clock interrupt vector value 00h No interrupt pending 02h Interrupt Source RTC oscillator failure Interrupt Flag RTCOFI...

Page 834: ...Register Description Bit Field Type Reset Description 15 0 BIN2BCDx RW 0h Read 16 bit BCD conversion of previously written 12 bit binary number Write 12 bit binary number to be converted 20 3 33 RTCB...

Page 835: ...Module REF_A The REF_A module is a general purpose reference system that is used to generate voltage references required for other analog modules available on a given device such as analog to digital...

Page 836: ...f the REF_A module is the bandgap from which all other reference voltages are derived by unity or noninverting gain stages The REFGEN subsystem inside the REF_A module consists of the bandgap the band...

Page 837: ...nother analog module is requesting sampled mode In other words static mode request always has higher priority than sampled mode request When the REFON bit is set the bandgap and the bandgap bias opera...

Page 838: ...ff The REFGENBUSY signal when asserted indicates that an analog module is using the reference and cannot have any of it settings changed For example during an active ADC14 conversion the reference vol...

Page 839: ...ANYREG_L refers to the lower byte of the register bits 0 through 7 The suffix _H ANYREG_H refers to the upper byte of the register bits 8 through 15 Table 21 1 REF_A Registers Offset Acronym Register...

Page 840: ...y 1b Reference generator busy 9 REFBGACT R 0h Reference bandgap active Read only 0b Reference bandgap buffer not active 1b Reference bandgap buffer active 8 REFGENACT R 0h Reference generator active R...

Page 841: ...0h Reserved 1 REFOUT RW 0h Reference output buffer Can be modified only when REFGENBUSY 0 0b Reference output not available externally 1b Reference output available externally If ADC14REFBURST 0 outpu...

Page 842: ...5 2019 Texas Instruments Incorporated Precision ADC Chapter 22 SLAU356I March 2015 Revised June 2019 Precision ADC This chapter describes the operation of the Precision ADC module Topic Page 22 1 Prec...

Page 843: ...imers Conversion initiation by software or timers Software selectable on chip reference voltage generation 1 2 V 1 45 V or 2 5 V with option to make available externally Software selectable internal o...

Page 844: ...C14CH3MAP 1 0 ADC14CH2MAP 1 0 ADC14CH1MAP 1 0 ADC14CH0MAP 1 0 ADC14TCMAP 1 0 ADC14BATMAP AMAX AMAX 1 AMAX 2 AMAX 3 AMAX 4 AMAX 5 MCLK 000 0 0 0 0 1 0 1 1 1 101 SYSCLK SHI_EN See Note Precision ADC Int...

Page 845: ...sion ADC core is configured by two control registers ADC14CTL0 and ADC14CTL1 The core is reset when ADC14ON 0 When ADC14ON 1 reset is removed and the core is ready to power up when a valid conversion...

Page 846: ...part of the port pin eliminates the parasitic current flow and reduces overall current consumption The PySELx bits provide the ability to disable the port pin input and output buffers 22 2 3 Voltage R...

Page 847: ...14CLK cycles for 8 bit 10 bit 12 bit and 14 bit resolution modes respectively The polarity of the SHI signal source can be inverted with the ADC14ISSH bit The SAMPCON signal controls the sample period...

Page 848: ...2 ADC14CLK cycles ADC14SHT0x selects the sampling time for ADC14MCTL8 to ADC14MCTL23 and ADC14SHT1x selects the sampling time for ADC14MCTL0 to ADC14MCTL7 and ADC14MCTL24 to ADC14MCTL31 Figure 22 4 Pu...

Page 849: ...Detector CMD The CMD has a unique common mode voltage detection circuit that allows VCM to be set to any value from 0 V to VREF without degrading device performance The detected common mode voltage is...

Page 850: ...to 8191 8000h to 7FFCh Vin Vin VREF to VREF 1 0 00 128 to 127 0 to 255 0000h to 00FFh 1 0 01 512 to 511 0 to 1023 0000h to 03FFh 1 0 10 2048 to 2047 0 to 4095 0000h to 0FFFh 1 0 11 8192 to 8192 0 to 1...

Page 851: ...n Feedback Copyright 2015 2019 Texas Instruments Incorporated Precision ADC 22 2 8 1 Single Channel Single Conversion Mode A single channel is sampled and converted once The ADC result is written to t...

Page 852: ...ight 2015 2019 Texas Instruments Incorporated Precision ADC 22 2 8 2 Sequence of Channels Mode Autoscan Mode In sequence of channels mode also referred to as autoscan mode a sequence of channels is sa...

Page 853: ...Operation 853 SLAU356I March 2015 Revised June 2019 Submit Documentation Feedback Copyright 2015 2019 Texas Instruments Incorporated Precision ADC 22 2 8 3 Repeat Single Channel Mode A single channel...

Page 854: ...Precision ADC Operation www ti com 854 SLAU356I March 2015 Revised June 2019 Submit Documentation Feedback Copyright 2015 2019 Texas Instruments Incorporated Precision ADC 22 2 8 4 Repeat Sequence of...

Page 855: ...single channel mode and then reset ADC14ENC 22 2 9 Window Comparator The window comparator allows to monitor analog signals without any CPU interaction It is enabled for the desired ADC14MEMx convers...

Page 856: ...ADC14INCHx MAX 1 where MAX is the maximum number of external ADC input channels for the device starting count at zero for the temperature sensor Any other configuration is done as if that external ch...

Page 857: ...d loops unwanted parasitic effects and noise Ground loops are formed when return current from the ADC flows through paths that are common with other analog or digital circuitry If care is not taken th...

Page 858: ...hannel conversions in sequence of channels conversion mode ADC14LOIFG ADC14INIFG and ADC14HIIFG for ADC14MEMx ADC14RDYIFG Precision ADC local buffered reference ready The ADC14RDYIFG is set when the P...

Page 859: ...or High Threshold 1 Register Read write 00003FFFh Section 22 3 6 018h to 094h ADC14MCTL0 to ADC14MCTL31 Memory Control 0 to Memory Control 31 Register Read write 00000000h Section 22 3 7 098h to 114h...

Page 860: ...by 64 29 27 ADC14SHSx RW 0h ADC14 sample and hold source select Can be modified only when ADC14ENC 0 000b ADC14SC bit 001b See device specific data sheet for source 010b See device specific data shee...

Page 861: ...only when ADC14ENC 0 00b Single channel single conversion 01b Sequence of channels 10b Repeat single channel 11b Repeat sequence of channels 16 ADC14BUSY R 0h ADC14 busy This bit indicates an active...

Page 862: ...et for minimum sampling time 7 ADC14MSC RW 0h ADC14 multiple sample and conversion Valid only for sequence or repeated modes 0b The sampling timer requires a rising edge of the SHI signal to trigger e...

Page 863: ...MAX 4 0b ADC input channel internal 2 is not selected 1b ADC input channel internal 2 is selected for ADC input channel MAX 4 25 ADC14CH1MAP RW 0h Controls internal channel 1 selection to ADC input ch...

Page 864: ...0b Binary unsigned Theoretically for ADC14DIF 0 and 14 bit mode the analog input voltage V REF results in 0000h and the analog input voltage V REF results in 3FFFh 1b Signed binary 2s complement left...

Page 865: ...6 Reserved r 0 r 0 r 0 r 0 r 0 r 0 r 0 r 0 15 14 13 12 11 10 9 8 ADC14LO0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 7 6 5 4 3 2 1 0 ADC14LO0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 Table 22 7 ADC14LO0 R...

Page 866: ...12 11 10 9 8 ADC14HI0 rw 0 rw 0 rw 1 rw 1 rw 1 rw 1 rw 1 rw 1 7 6 5 4 3 2 1 0 ADC14HI0 rw 1 rw 1 rw 1 rw 1 rw 1 rw 1 rw 1 rw 1 Table 22 8 ADC14HI0 Register Description Bit Field Type Reset Descriptio...

Page 867: ...6 Reserved r 0 r 0 r 0 r 0 r 0 r 0 r 0 r 0 15 14 13 12 11 10 9 8 ADC14LO1 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 7 6 5 4 3 2 1 0 ADC14LO1 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 Table 22 9 ADC14LO1 R...

Page 868: ...12 11 10 9 8 ADC14HI1 rw 0 rw 0 rw 1 rw 1 rw 1 rw 1 rw 1 rw 1 7 6 5 4 3 2 1 0 ADC14HI1 rw 1 rw 1 rw 1 rw 1 rw 1 rw 1 rw 1 rw 1 Table 22 10 ADC14HI1 Register Description Bit Field Type Reset Descripti...

Page 869: ...an be modified only when ADC14ENC 0 0b Use window comparator thresholds 0 ADC14LO0 and ADC14HI0 1b Use window comparator thresholds 1 ADC14LO1 and ADC14HI1 14 ADC14WINC RW 0h Comparator window enable...

Page 870: ...14DIF 1 Ain A10 Ain A11 01011b If ADC14DIF 0 A11 If ADC14DIF 1 Ain A10 Ain A11 01100b If ADC14DIF 0 A12 If ADC14DIF 1 Ain A12 Ain A13 01101b If ADC14DIF 0 A13 If ADC14DIF 1 Ain A12 Ain A13 01110b If A...

Page 871: ...ned If ADC14DF 0 unsigned binary The 14 bit conversion results are right aligned Bit 13 is the MSB Bits 15 14 are 0 in 14 bit mode bits 15 12 are 0 in 12 bit mode bits 15 10 are 0 in 10 bit mode and b...

Page 872: ...Interrupt enable Enables or disables the interrupt request for the ADC14IFG31 bit 0b Interrupt disabled 1b Interrupt enabled 30 ADC14IE30 RW 0h Interrupt enable Enables or disables the interrupt requ...

Page 873: ...enabled 18 ADC14IE18 RW 0h Interrupt enable Enables or disables the interrupt request for the ADC14IFG18 bit 0b Interrupt disabled 1b Interrupt enabled 17 ADC14IE17 RW 0h Interrupt enable Enables or...

Page 874: ...errupt enabled 6 ADC14IE6 RW 0h Interrupt enable Enables or disables the interrupt request for the ADC14IFG6 bit 0b Interrupt disabled 1b Interrupt enabled 5 ADC14IE5 RW 0h Interrupt enable Enables or...

Page 875: ...ads as 0 6 ADC14RDYIE RW 0h ADC14 local buffered reference ready interrupt enable 0b Interrupt disabled 1b Interrupt enabled 5 ADC14TOVIE RW 0h ADC14 conversion time overflow interrupt enable 0b Inter...

Page 876: ...or when the corresponding bit in the ADC14CLRIFGR0 register is set to 1 0b No interrupt pending 1b Interrupt pending 29 ADC14IFG29 R 0h ADC14MEM29 interrupt flag This bit is set to 1 when ADC14MEM29...

Page 877: ...DC14CLRIFGR0 register is set to 1 0b No interrupt pending 1b Interrupt pending 19 ADC14IFG19 R 0h ADC14MEM19 interrupt flag This bit is set to 1 when ADC14MEM19 is loaded with a conversion result This...

Page 878: ...bit in the ADC14CLRIFGR0 register is set to 1 0b No interrupt pending 1b Interrupt pending 8 ADC14IFG8 R 0h ADC14MEM8 interrupt flag This bit is set to 1 when ADC14MEM8 is loaded with a conversion res...

Page 879: ...ADC14CLRIFGR0 register is set to 1 0b No interrupt pending 1b Interrupt pending 1 ADC14IFG1 R 0h ADC14MEM1 interrupt flag This bit is set to 1 when ADC14MEM1 is loaded with a conversion result This b...

Page 880: ...it is reset to 0 by IV register read or when corresponding bit in ADC14CLRIFGR1 is set to 1 0b No interrupt pending 1b Interrupt pending 4 ADC14OVIFG R 0h ADC14MEMx overflow interrupt flag This bit is...

Page 881: ...w 0 w 0 w 0 7 6 5 4 3 2 1 0 CLRADC14IFG 7 CLRADC14IFG 6 CLRADC14IFG 5 CLRADC14IFG 4 CLRADC14IFG 3 CLRADC14IFG 2 CLRADC14IFG 1 CLRADC14IFG 0 w 0 w 0 w 0 w 0 w 0 w 0 w 0 w 0 Table 22 17 ADC14CLRIFGR0 R...

Page 882: ...clear ADC14IFG17 0b no effect 1b clear pending interrupt flag 16 CLRADC14IFG16 W 0h clear ADC14IFG16 0b no effect 1b clear pending interrupt flag 15 CLRADC14IFG15 W 0h clear ADC14IFG15 0b no effect 1...

Page 883: ...r pending interrupt flag 5 CLRADC14IFG5 W 0h clear ADC14IFG5 0b no effect 1b clear pending interrupt flag 4 CLRADC14IFG4 W 0h clear ADC14IFG4 0b no effect 1b clear pending interrupt flag 3 CLRADC14IFG...

Page 884: ...FG CLRADC14HIIF G CLRADC14LOI FG CLRADC14INIF G Reserved r 0 w 0 w 0 w 0 w 0 w 0 w 0 r 0 Table 22 18 ADC14CLRIFGR1 Register Description Bit Field Type Reset Description 31 7 Reserved R 0h Reserved Alw...

Page 885: ...Register offset 154h reset 00000000h ADC14 Interrupt Vector Register Figure 22 27 ADC14IV Register 31 30 29 28 27 26 25 24 ADC14IVx rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 23 22 21 20 19 18 17 16 ADC1...

Page 886: ...rupt flag Interrupt Flag ADC14IFG9 20h Interrupt Source ADC14MEM10 interrupt flag Interrupt Flag ADC14IFG10 22h Interrupt Source ADC14MEM11 interrupt flag Interrupt Flag ADC14IFG11 24h Interrupt Sourc...

Page 887: ...or E Module COMP_E Chapter 23 SLAU356I March 2015 Revised June 2019 Comparator E Module COMP_E Comparator_E is an analog voltage comparator with general comparator functionality for up to 16 channels...

Page 888: ...e COMP_E module supports precision slope analog to digital conversions supply voltage supervision and monitoring of external analog signals Features of COMP_E include Inverting and noninverting termin...

Page 889: ...and CEIMSELx bits The comparator terminal inputs can be controlled individually The CEIPSELx and CEIMSELx bits allow Application of an external signal to the V and V terminals of the comparator Routi...

Page 890: ...ld be used as a sampling time With 3 Tau the sampling capacitor is charged to approximately 95 of the input signals voltage level with 5 Tau it is charged to more than 99 and with 10 Tau the sampled v...

Page 891: ...orporated Comparator E Module COMP_E Figure 23 3 RC Filter Response at the Output of the Comparator 23 2 6 Reference Voltage Generator Figure 23 4 shows the Comparator_E reference block diagram Figure...

Page 892: ...mption The CEPDx bits when set disable the corresponding Px y input buffer as shown in Figure 23 5 When current consumption is critical any Px y pin connected to analog signals should be disabled with...

Page 893: ...d discharges the capacitor through Rref One output discharges capacitor through Rmeas The terminal is connected to the positive terminal of the capacitor The terminal is connected to a reference level...

Page 894: ...f ref meas meas ref ref V R C ln V N N V R C ln V N R N R N R R N COMP_E Operation www ti com 894 SLAU356I March 2015 Revised June 2019 Submit Documentation Feedback Copyright 2015 2019 Texas Instrume...

Page 895: ...ction 23 3 1 02h CExCTL1 Comparator_E control 1 Read write Half word 0000h Section 23 3 2 04h CExCTL2 Comparator_E control 2 Read write Half word 0000h Section 23 3 3 06h CExCTL3 Comparator_E control...

Page 896: ...pe Reset Description 15 CEIMEN RW 0h Channel input enable for the V terminal of the comparator 0b Selected analog input channel for V terminal is disabled 1b Selected analog input channel for V termin...

Page 897: ...comparator on When the comparator is turned off the Comparator consumes no power 0b Off 1b On 9 8 CEPWRMD RW 0h Power Mode 00b High speed mode 01b Normal mode 10b Ultra low power mode 11b Reserved 7...

Page 898: ...as shared reference voltage input 10b 2 0 V is selected as shared reference voltage input 11b 2 5 V is selected as shared reference voltage input 12 8 CEREF1 RW 0h Reference resistor tap 1 This regist...

Page 899: ...omparator_E The bit CEPD13 disables the port of the comparator channel 13 0b The input buffer is enabled 1b The input buffer is disabled 12 CEPD12 RW 0h Port disable These bits individually disable th...

Page 900: ...able These bits individually disable the input buffer for the pins of the port associated with Comparator_E The bit CEPD4 disables the port of the comparator channel 4 0b The input buffer is enabled 1...

Page 901: ...eserved R 0h Reserved Always reads as 0 9 CEIIE RW 0h Comparator output interrupt enable inverted polarity 0b Interrupt disabled 1b Interrupt enabled 8 CEIE RW 0h Comparator output interrupt enable 0b...

Page 902: ...xIV Register Description Bit Field Type Reset Description 15 0 CEIV R 0h Comparator interrupt vector word register The interrupt vector register reflects only interrupt flags whose interrupt enable bi...

Page 903: ...ersal Serial Communication Interface eUSCI UART Mode The enhanced universal serial communication interface A eUSCI_A supports multiple serial communication modes with one hardware module This chapter...

Page 904: ...rnal system through two external pins UCAxRXD and UCAxTXD UART mode is selected when the UCSYNC bit is cleared UART mode features include 7 bit or 8 bit data with odd even or no parity Independent tra...

Page 905: ...DA Decoder UCIRRXFE UCIRRXFLx 6 Transmit Buffer UCAxTXBUF Transmit State Machine UCTXADDR UCTXBRK Transmit Shift Register UCPEN UCPAR UCMSB UC7BIT UCIREN UCIRTXPLx 6 0 1 IrDA Encoder UCAxTXD Transmit...

Page 906: ...l eUSCI_A registers with UCSWRST 1 including UCAxCTL1 3 Configure ports 4 Clear UCSWRST with software 5 Enable interrupts optional with UCRXIE or UCTXIE 24 3 2 Character Format The UART character form...

Page 907: ...rs are received When UCDORM is cleared during the reception of a character the receive interrupt flag is set after the reception completed The UCDORM bit is not modified automatically by the eUSCI_A h...

Page 908: ...it is received but has a framing error or parity error the character is not transferred into UCAxRXBUF and UCRXIFG is not set If an address is received user software can validate the address and must...

Page 909: ...time the synch timeout error flag UCSTOE is set The result can be read after the receive interrupt flag UCRXIFG is set Figure 24 6 Auto Baud Rate Detection Synch Field The UCDORM bit is used to contr...

Page 910: ...re bit shaping for IrDA communication 24 3 5 1 IrDA Encoding The encoder sends a pulse for every zero bit in the transmit bit stream coming from the UART see Figure 24 7 The pulse duration is defined...

Page 911: ...E A parity error is a mismatch between the number of 1s in a character and the value of the parity bit When an address bit is included in the character it is included in the parity calculation When a...

Page 912: ...CI_A from being accidentally started Any glitch on UCAxRXD shorter than the deglitch time tt is ignored by the eUSCI_A and further action is initiated as shown in Figure 24 8 see the device specific d...

Page 913: ...e with higher frequencies and higher prescaler settings causes the majority votes to be taken in an increasingly smaller window and thus decrease the benefit of the majority vote In low frequency mode...

Page 914: ...he maximum eUSCI_A baud rate is 1 16 the UART source clock frequency BRCLK Modulation for BITCLK16 is based on the UCBRFx setting see Table 24 3 A 1 in the table indicates that the corresponding BITCL...

Page 915: ...be used as a lookup table for finding the correct UCBRSx modulation pattern for the corresponding fractional part of N The values there are optimized for transmitting 1 The UCBRSx setting in one row...

Page 916: ...ngs Tbit TX i 1 fBRCLK UCBRx mUCBRSx i Where mUCBRSx i Modulation of bit i of UCBRSx 24 3 11 2 Oversampling Baud Rate Mode Bit Timing In oversampling baud rate mode calculation of the length of bit i...

Page 917: ...eal sampling time tbit RX i is equal to the sum of all previous bits according to the formulas shown in the transmit timing section plus one half BITCLK for the current bit i plus the synchronization...

Page 918: ...0000 9600 1 6 8 0x20 0 48 0 64 1 04 1 04 1000000 19200 1 3 4 0x2 0 8 0 96 1 84 1 84 1000000 38400 1 1 10 0x0 0 1 76 0 3 44 1000000 57600 0 17 0x4A 2 72 2 56 3 76 7 28 1000000 115200 0 8 0xD6 7 36 5 6...

Page 919: ...1 0xB5 0 31 0 31 0 53 0 78 16777216 230400 1 4 8 0xEE 0 75 0 74 2 0 87 16777216 460800 1 2 4 0x92 1 62 1 37 3 56 2 06 20000000 9600 1 130 3 0x25 0 02 0 03 0 0 07 20000000 19200 1 65 1 0xD6 0 06 0 03...

Page 920: ...G Transmit complete interrupt This flag is set after the complete UART byte in the internal shift register including STOP bit got shifted out and UCAxTXBUF is empty 24 3 15 4 UCAxIV Interrupt Vector G...

Page 921: ...ransfers when the transmit buffer UCAxTXBUF is empty or when data was received in the UCAxRXBUF buffer The DMA trigger signals correspond to the UCTXIFG transmit interrupt flag and the UCRXIFG receive...

Page 922: ...USCI_Ax Baud Rate Control 0 07h UCAxBR1 eUSCI_Ax Baud Rate Control 1 08h UCAxMCTLW eUSCI_Ax Modulation Control Word Section 24 4 4 0Ah UCAxSTATW eUSCI_Ax Status Section 24 4 5 0Ch UCAxRXBUF eUSCI_Ax R...

Page 923: ...parity is disabled 0b Odd parity 1b Even parity 13 UCMSB RW 0h MSB first select Controls the direction of the receive and transmit shift register 0b LSB first 1b MSB first 12 UC7BIT RW 0h Character l...

Page 924: ...frame transmitted is an address 1 UCTXBRK RW 0h Transmit break Transmits a break with the next write to the transmit buffer In UART mode with automatic baud rate detection 055h must be written into U...

Page 925: ...rate generator 24 4 4 UCAxMCTLW Register eUSCI_Ax Modulation Control Word Register Figure 24 15 UCAxMCTLW Register 15 14 13 12 11 10 9 8 UCBRSx rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 7 6 5 4 3 2 1 0...

Page 926: ...leared automatically when UCxRXBUF is read and must not be cleared by software Otherwise it does not function correctly 0b No error 1b Overrun error occurred 4 UCPE RW 0h Parity error flag When UCPEN...

Page 927: ...e last received character from the receive shift register Reading UCAxRXBUF resets the receive error bits the UCADDR or UCIDLE bit and UCRXIFG In 7 bit data mode UCAxRXBUF is LSB justified and the MSB...

Page 928: ...n UCSWRST 1 Table 24 15 UCAxABCTL Register Description Bit Field Type Reset Description 15 6 Reserved R 0h Reserved 5 4 UCDELIMx RW 0h Break synch delimiter length 00b 1 bit time 01b 2 bit times 10b 3...

Page 929: ...scription Bit Field Type Reset Description 15 10 UCIRRXFLx RW 0h Receive filter length The minimum pulse length for receive is given by tMIN UCIRRXFLx 4 2 fIRTXCLK 9 UCIRRXPL RW 0h IrDA receive input...

Page 930: ...r 0 r 0 r 0 r 0 7 6 5 4 3 2 1 0 Reserved UCTXCPTIE UCSTTIE UCTXIE UCRXIE r 0 r 0 r 0 r 0 rw 0 rw 0 rw 0 rw 0 Table 24 17 UCAxIE Register Description Bit Field Type Reset Description 15 4 Reserved R 0h...

Page 931: ...Register Description Bit Field Type Reset Description 15 4 Reserved R 0h Reserved 3 UCTXCPTIFG RW 0h Transmit complete interrupt flag UCTXCPTIFG is set when the entire byte in the internal shift regis...

Page 932: ...CIVx r0 r0 r0 r0 r0 r0 r0 r0 7 6 5 4 3 2 1 0 UCIVx r0 r0 r0 r0 r 0 r 0 r 0 r0 Table 24 19 UCAxIV Register Description Bit Field Type Reset Description 15 0 UCIVx R 0h eUSCI_A interrupt vector value 00...

Page 933: ...erface eUSCI SPI Mode The enhanced universal serial communication interfaces eUSCI_A and eUSCI_B support multiple serial communication modes with one hardware module This chapter discusses the operati...

Page 934: ...s the device to an external system through three or four pins UCxSIMO UCxSOMI UCxCLK and UCxSTE SPI mode is selected when the UCSYNC bit is set and SPI mode 3 pin or 4 pin is selected with the UCMODEx...

Page 935: ...er UCMSB UC7BIT BRCLK Set UCxRXIFG Set UCxTXIFG 0 1 UCLISTEN Clock Direction Phase and Polarity UCCKPH UCCKPL UCxSIMO UCxCLK Set UCOE Transmit Enable Control UCSTEM UCxSTE Set UCFE 2 UCMODEx www ti co...

Page 936: ...transmit enable Used in 4 pin mode to allow multiple masters on a single bus Not used in 3 pin mode Table 25 1 describes the UCxSTE operation Table 25 1 UCxSTE Operation UCMODEx UCxSTE Active State UC...

Page 937: ...initiates data transfer when data is moved to the transmit data buffer UCxTXBUF The UCxTXBUF data is moved to the transmit TX shift register when the TX shift register is empty initiating data transfe...

Page 938: ...ten into UCxTXBUF to be transferred when UCxSTE transitions back to the master active state The UCxSTE input signal is not used in 3 pin master mode 25 3 3 2 4 Pin SPI Master Mode UCSTEM 1 If UCSTEM 1...

Page 939: ...smit Enable In master mode writing to UCxTXBUF activates the bit clock generator and the data begins to transmit In slave mode transmission begins when a master provides a clock and in 4 pin mode when...

Page 940: ...on is useful if the eUSCI is transmitting or receiving data at a very slow rate and the application should enter low power mode at the expense of a packet of data being lost Refer to the Power Control...

Page 941: ...tor The interrupt vector register UCxIV is used to determine which flag requested an interrupt The highest priority enabled interrupt generates a number in the UCxIV register that can be evaluated by...

Page 942: ...l 1 01h UCAxCTL0 eUSCI_Ax Control 0 06h UCAxBRW eUSCI_Ax Bit Rate Control Word Section 25 4 2 06h UCAxBR0 eUSCI_Ax Bit Rate Control 0 07h UCAxBR1 eUSCI_Ax Bit Rate Control 1 0Ah UCAxSTATW eUSCI_Ax Sta...

Page 943: ...ols the direction of the receive and transmit shift register 0b LSB first 1b MSB first 12 UC7BIT RW 0h Character length Selects 7 bit or 8 bit character length 0b 8 bit data 1b 7 bit data 11 UCMST RW...

Page 944: ...rial Communication Interface eUSCI SPI Mode 25 4 2 UCAxBRW Register eUSCI_Ax Bit Rate Control Register 1 Figure 25 6 UCAxBRW Register 15 14 13 12 11 10 9 8 UCBRx rw rw rw rw rw rw rw rw 7 6 5 4 3 2 1...

Page 945: ...0h Listen enable The UCLISTEN bit selects loopback mode 0b Disabled 1b Enabled The transmitter output is internally fed back to the receiver 6 UCFE RW 0h Framing error flag This bit indicates a bus co...

Page 946: ...UCAxRXBUF Register 15 14 13 12 11 10 9 8 Reserved r0 r0 r0 r0 r0 r0 r0 r0 7 6 5 4 3 2 1 0 UCRXBUFx rw rw rw rw rw rw rw rw Table 25 6 UCAxRXBUF Register Description Bit Field Type Reset Description 15...

Page 947: ...9 UCAxTXBUF Register 15 14 13 12 11 10 9 8 Reserved r0 r0 r0 r0 r0 r0 r0 r0 7 6 5 4 3 2 1 0 UCTXBUFx rw rw rw rw rw rw rw rw Table 25 7 UCAxTXBUF Register Description Bit Field Type Reset Description...

Page 948: ...x Interrupt Enable Register Figure 25 10 UCAxIE Register 15 14 13 12 11 10 9 8 Reserved r0 r0 r0 r0 r0 r0 r0 r0 7 6 5 4 3 2 1 0 Reserved UCTXIE UCRXIE r 0 r 0 r 0 r 0 r 0 r 0 rw 0 rw 0 Table 25 8 UCAx...

Page 949: ...ter 15 14 13 12 11 10 9 8 Reserved r0 r0 r0 r0 r0 r0 r0 r0 7 6 5 4 3 2 1 0 Reserved UCTXIFG UCRXIFG r 0 r 0 r 0 r 0 r 0 r 0 rw 1 rw 0 Table 25 9 UCAxIFG Register Description Bit Field Type Reset Descr...

Page 950: ...tor Register Figure 25 12 UCAxIV Register 15 14 13 12 11 10 9 8 UCIVx r0 r0 r0 r0 r0 r0 r0 r0 7 6 5 4 3 2 1 0 UCIVx r0 r0 r0 r 0 r 0 r 0 r 0 r0 Table 25 10 UCAxIV Register Description Bit Field Type R...

Page 951: ...ol 1 01h UCBxCTL0 eUSCI_Bx Control 0 06h UCBxBRW eUSCI_Bx Bit Rate Control Word Section 25 5 2 06h UCBxBR0 eUSCI_Bx Bit Rate Control 0 07h UCBxBR1 eUSCI_Bx Bit Rate Control 1 08h UCBxSTATW eUSCI_Bx St...

Page 952: ...ols the direction of the receive and transmit shift register 0b LSB first 1b MSB first 12 UC7BIT RW 0h Character length Selects 7 bit or 8 bit character length 0b 8 bit data 1b 7 bit data 11 UCMST RW...

Page 953: ...w 0 r0 r0 r0 r0 r 0 Modify only when UCSWRST 1 Table 25 14 UCBxSTATW Register Description Bit Field Type Reset Description 15 8 Reserved R 0h Reserved 7 UCLISTEN RW 0h Listen enable The UCLISTEN bit s...

Page 954: ...ssible and contains the last received character from the receive shift register Reading UCxRXBUF resets the receive error bits and UCRXIFG In 7 bit data mode UCxRXBUF is LSB justified and the MSB is a...

Page 955: ...RW 0h Transmit interrupt enable 0b Interrupt disabled 1b Interrupt enabled 0 UCRXIE RW 0h Receive interrupt enable 0b Interrupt disabled 1b Interrupt enabled 25 5 7 UCBxIFG Register eUSCI_Bx Interrupt...

Page 956: ...r Register Figure 25 20 UCBxIV Register 15 14 13 12 11 10 9 8 UCIVx r0 r0 r0 r0 r0 r0 r0 r0 7 6 5 4 3 2 1 0 UCIVx r0 r0 r0 r 0 r 0 r 0 r 0 r0 Table 25 19 UCBxIV Register Description Bit Field Type Res...

Page 957: ...ed Universal Serial Communication Interface eUSCI I2 C Mode The enhanced universal serial communication interface B eUSCI_B supports multiple serial communication modes with one hardware module This c...

Page 958: ...en the device and I2 C compatible devices connected by the two wire I2 C serial bus External components attached to the I2 C bus serially transmit or receive serial data to or from the eUSCI_B module...

Page 959: ...9 Submit Documentation Feedback Copyright 2015 2019 Texas Instruments Incorporated Enhanced Universal Serial Communication Interface eUSCI I2 C Mode Figure 26 1 eUSCI_B Block Diagram I2 C Mode 26 3 eU...

Page 960: ...he eUSCI_B module should be done when UCSWRST is set to avoid unpredictable behavior Setting UCSWRST in I2 C mode has the following effects I2 C communication stops SDA and SCL are high impedance UCBx...

Page 961: ...P Data on SDA must be stable during the high period of SCL see Figure 26 4 The high and low state of SDA can change only when SCL is low otherwise START or STOP conditions are generated Figure 26 4 Bi...

Page 962: ...sent out with the new data direction specified by the R W bit Figure 26 7 shows the RESTART condition Figure 26 7 I2 C Module Addressing Format With Repeated START Condition 26 3 4 I2 C Module Operati...

Page 963: ...eUSCI_B slave address 26 3 4 1 1 I2 C Slave Transmitter Mode Slave transmitter mode is entered when the slave address transmitted by the master is identical to its own address with a set R W bit The...

Page 964: ...e clock pulses that are generated by the master device The slave device does not generate the clock but it can hold SCL low if intervention of the CPU is required after a byte has been received If the...

Page 965: ...Copyright 2015 2019 Texas Instruments Incorporated Enhanced Universal Serial Communication Interface eUSCI I2 C Mode If the master generates a repeated START condition the eUSCI_B I2 C state machine...

Page 966: ...26 3 4 2 Master Mode The eUSCI_B module is configured as an I2 C master by selecting the I2 C mode with UCMODEx 11 and UCSYNC 1 and setting the UCMST bit When the master is part of a multi master syst...

Page 967: ...TXSTT bit is not set Setting UCTXSTP generates a STOP condition after the next acknowledge from the slave If UCTXSTP is set during the transmission of the slave address or while the eUSCI_B module wai...

Page 968: ...continues A UCALIFG 1 UCMST 0 UCTR 0 Receiver UCSTTIFG 1 UCGC 1 if general call USCI continues as Slave Receiver Not acknowledge received after a data byte UCTXSTT 0 UCTXSTP 0 UCTXSTP 0 UCALIFG 1 UCM...

Page 969: ...is set If UCBxRXBUF is not read the master holds the bus during reception of the last data bit and until the UCBxRXBUF is read If the slave does not acknowledge the transmitted address the not acknow...

Page 970: ...TR 0 Receiver 2 UCTXSTT 1 Arbitration lost in slave address or data byte A Other master continues UCALIFG 1 UCMST 0 Arbitration lost and addressed as slave Other master continues A UCALIFG 1 UCMST 0 U...

Page 971: ...he bus an arbitration procedure is invoked Figure 26 15 shows the arbitration procedure between two devices The arbitration procedure uses the data presented on SDA by the competing transmitters The f...

Page 972: ...n factor of the eUSCI_B clock source BRCLK The maximum bit clock that can be used in single master mode is fBRCLK 4 In multi master mode the maximum bit clock is fBRCLK 8 The BITCLK frequency is given...

Page 973: ...medied by using the early Transmit Interrupt see Section 26 3 10 2 26 3 6 3 Clock Low Time out The UCCLTOIFG interrupt allows the software to react if the clock is low longer than a defined time It is...

Page 974: ...hes more than one of the slave address registers The priority decreases with the index number of the address register so that UCBxI2COA0 in combination with the address mask has the lowest priority Wh...

Page 975: ...e to accept a new byte When operating as a slave with multiple slave addresses the UCTXIFGx flags are set corresponding to which address was received before If for example the slave address specified...

Page 976: ...oftware if wanted The UCBIT9IFG is not set for address information UCBCNTIFG Byte counter interrupt This flag is set when the byte counter value reaches the value defined in UCBxTBCNT and UCASTPx 01 o...

Page 977: ...I_Bx Status 09h UCBxBCNT eUSCI_Bx Byte Counter 0Ah UCBxTBCNT eUSCI_Bx Byte Counter Threshold Section 26 4 5 0Ch UCBxRXBUF eUSCI_Bx Receive Buffer Section 26 4 6 0Eh UCBxTXBUF eUSCI_Bx Transmit Buffer...

Page 978: ...in the system The address compare unit is disabled 1b Multi master environment 12 Reserved R 0h Reserved 11 UCMST RW 0h Master mode select When a master loses arbitration in a multi master environment...

Page 979: ...Transmit STOP condition in master mode Ignored in slave mode In master receiver mode the STOP condition is preceded by a NACK UCTXSTP is automatically cleared after STOP is generated This bit is a don...

Page 980: ...cycles approximately 34 ms 5 UCSTPNACK RW 0h The UCSTPNACK bit allows to make the eUSCI_B master acknowledge the last byte in master receiver mode as well This is not conform to the I2C specification...

Page 981: ...tion Feedback Copyright 2015 2019 Texas Instruments Incorporated Enhanced Universal Serial Communication Interface eUSCI I2 C Mode Table 26 5 UCBxCTLW1 Register Description continued Bit Field Type Re...

Page 982: ...5 14 13 12 11 10 9 8 UCBCNTx r 0 r 0 r 0 r 0 r 0 r 0 r 0 r 0 7 6 5 4 3 2 1 0 Reserved UCSCLLOW UCGC UCBBUSY Reserved r0 r 0 r 0 r 0 r 0 r0 r0 r0 Table 26 7 UCBxSTATW Register Description Bit Field Typ...

Page 983: ...BCNT Register 15 14 13 12 11 10 9 8 Reserved r0 r0 r0 r0 r0 r0 r0 r0 7 6 5 4 3 2 1 0 UCTBCNTx rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 Modify only when UCSWRST 1 Table 26 8 UCBxTBCNT Register Descripti...

Page 984: ...R 0h Reserved 7 0 UCRXBUFx R 0h The receive data buffer is user accessible and contains the last received character from the receive shift register Reading UCBxRXBUF resets the UCRXIFGx flags 26 4 7...

Page 985: ...5 UCGCEN RW 0h General call response enable This bit is only available in UCBxI2COA0 Modify only when UCSWRST 1 0b Do not respond to a general call 1b Respond to a general call 14 11 Reserved R 0h Res...

Page 986: ...cal address of the eUSCIx_B I2C controller The address is right justified In 7 bit addressing mode bit 6 is the MSB and bits 9 7 are ignored In 10 bit addressing mode bit 9 is the MSB Modify only when...

Page 987: ...fy only when UCSWRST 1 0b The slave address defined in I2COA3 is disabled 1b The slave address defined in I2COA3 is enabled 9 0 I2COA3 RW 0h I2C own address The I2COA3 bits contain the local address o...

Page 988: ...a don t care when comparing the address on the bus to the own address Using this method it is possible to react on more than one slave address When all bits of ADDMASKx are set the address mask featur...

Page 989: ...h Transmit interrupt enable 3 0b Interrupt disabled 1b Interrupt enabled 12 UCRXIE3 RW 0h Receive interrupt enable 3 0b Interrupt disabled 1b Interrupt enabled 11 UCTXIE2 RW 0h Transmit interrupt enab...

Page 990: ...munication Interface eUSCI I2 C Mode Table 26 18 UCBxIE Register Description continued Bit Field Type Reset Description 2 UCSTTIE RW 0h START condition interrupt enable 0b Interrupt disabled 1b Interr...

Page 991: ...defined in UCBxI2COA3 was on the bus in the same frame 0b No interrupt pending 1b Interrupt pending 11 UCTXIFG2 RW 0h eUSCI_B transmit interrupt flag 2 UCTXIFG2 is set when UCBxTXBUF is empty in slave...

Page 992: ...t pending 1b Interrupt pending 3 UCSTPIFG RW 0h STOP condition interrupt flag 0b No interrupt pending 1b Interrupt pending 2 UCSTTIFG RW 0h START condition interrupt flag 0b No interrupt pending 1b In...

Page 993: ...upt Priority Highest 04h Interrupt Source Not acknowledgment Interrupt Flag UCNACKIFG 06h Interrupt Source Start condition received Interrupt Flag UCSTTIFG 08h Interrupt Source Stop condition received...

Page 994: ...LCD_F Controller Chapter 27 SLAU356I March 2015 Revised June 2019 LCD_F Controller The LCD_F controller drives static and 2 mux to 8 mux segment LCDs This chapter describes the LCD_F controller Topic...

Page 995: ...or 1 3 bias 4 mux 1 2 bias or 1 3 bias 5 mux 1 3 bias or 1 4 bias 6 mux 1 3 bias or 1 4 bias 7 mux 1 3 bias or 1 4 bias 8 mux 1 3 bias or 1 4 bias Table 27 1 lists the differences among LCD_B LCD_C LC...

Page 996: ...MCLK LCDANMEN LCDANMSTP LCDMXx LCD2B LCDREXT R03EXT LCDEXTBIAS LCDCLRBM LCDCLRRM LCDANMCLR LCDSON LCDCSSELx LCDSx V1 V2 V3 V4 V5 LCDSSEL LCD_F Controller Introduction www ti com 996 SLAU356I March 201...

Page 997: ...lting fLCD frequency is calculated by Equation 14 14 The proper fLCD frequency depends on the LCD s requirement for framing frequency and the LCD multiplex rate It is calculated by Equation 15 fLCD 2...

Page 998: ...ng the LCDANMLOOPIE bit enables the interrupt 27 2 4 Memory Each memory bit corresponds to one LCD segment or is not used depending on the mode To turn on an LCD segment its corresponding memory bit i...

Page 999: ...following sections 27 2 5 1 Configuration of Port Pin as LCD Output LCD segment common and Rxx functions are multiplexed with digital and analog I O functions at the device level The LCD segment or c...

Page 1000: ...in LCDCSSELx register must be set to 1 The corresponding LCDMx register is then used to configure the associated LCD pin to have a specific COMx functionality as described in the following section 27...

Page 1001: ...gments or all segments go blank at the next frame boundary and stay off for half of a BLKCLK period Then they go active at the next frame boundary and stay on for another half BLKCLK period before the...

Page 1002: ...Mode L0 COM0 COM1 COM2 COM3 COM4 COM5 COM6 8 mux Mode L0 COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 When animation is enabled by setting the LCDANMEN bit the L0 to Lx bits x depending on mux mode as def...

Page 1003: ...nd Operation 1003 SLAU356I March 2015 Revised June 2019 Submit Documentation Feedback Copyright 2015 2019 Texas Instruments Incorporated LCD_F Controller Figure 27 4 Animation Memory 27 2 5 5 1 Timing...

Page 1004: ...in 15 seconds NOTE Animation Frequency Restrictions The animation frequency must be smaller than the frame frequency fFrame The animation frequency should only be changed when LCDANMEN 0 27 2 5 6 LCD...

Page 1005: ...ternal pins if LCDREXT 1 To source the bias voltages V2 to V4 externally LCDEXTBIAS is set This also disables the internal bias generation Typically an equally weighted resistor divider is used with r...

Page 1006: ...he output waveforms V1 VCC together with the selected mode and biasing determine the contrast and the contrast ratio of the LCD The contrast ratio depends on the used LCD display and the selected bias...

Page 1007: ...ture and Operation 1007 SLAU356I March 2015 Revised June 2019 Submit Documentation Feedback Copyright 2015 2019 Texas Instruments Incorporated LCD_F Controller 27 2 5 7 Static Mode In static mode each...

Page 1008: ...nd Operation www ti com 1008 SLAU356I March 2015 Revised June 2019 Submit Documentation Feedback Copyright 2015 2019 Texas Instruments Incorporated LCD_F Controller 27 2 5 8 2 Mux Mode In 2 mux mode e...

Page 1009: ...Architecture and Operation 1009 SLAU356I March 2015 Revised June 2019 Submit Documentation Feedback Copyright 2015 2019 Texas Instruments Incorporated LCD_F Controller 27 2 5 9 3 Mux Mode In 3 mux mo...

Page 1010: ...re and Operation www ti com 1010 SLAU356I March 2015 Revised June 2019 Submit Documentation Feedback Copyright 2015 2019 Texas Instruments Incorporated LCD_F Controller 27 2 5 10 4 Mux Mode In 4 mux m...

Page 1011: ...r Architecture and Operation 1011 SLAU356I March 2015 Revised June 2019 Submit Documentation Feedback Copyright 2015 2019 Texas Instruments Incorporated LCD_F Controller 27 2 5 11 6 Mux Mode In 6 mux...

Page 1012: ...cture and Operation www ti com 1012 SLAU356I March 2015 Revised June 2019 Submit Documentation Feedback Copyright 2015 2019 Texas Instruments Incorporated LCD_F Controller 27 2 5 12 8 Mux Mode In 8 mu...

Page 1013: ...015 Revised June 2019 Submit Documentation Feedback Copyright 2015 2019 Texas Instruments Incorporated LCD_F Controller Figure 27 13 shows some example 8 mux 1 3 bias waveforms with LCDLP 1 With LCDLP...

Page 1014: ...ff V2 V2 V2 V2 V1 V1 V1 V1 V5 V5 V5 V5 fframe LCD_F Controller Architecture and Operation www ti com 1014 SLAU356I March 2015 Revised June 2019 Submit Documentation Feedback Copyright 2015 2019 Texas...

Page 1015: ...MCTL LCD_F blinking and memory control Read write 00000000h Section 27 3 2 008h LCDVCTL LCD_F voltage control Read write 00000000h Section 27 3 3 00Ch LCDPCTL0 LCD_F port control 0 Read write 00000000...

Page 1016: ...on 27 3 13 132h LCDM18 LCD memory 18 L18 Read write Unchanged Section 27 3 13 133h LCDM19 LCD memory 19 L19 Read write Unchanged Section 27 3 13 134h LCDM20 LCD memory 20 L20 Read write Unchanged Sect...

Page 1017: ...3h LCDM51 LCD memory 51 L51 Read write Unchanged Section 27 3 13 154h LCDM52 LCD memory 52 L52 Read write Unchanged Section 27 3 13 155h LCDM53 LCD memory 53 L53 Read write Unchanged Section 27 3 13 1...

Page 1018: ...king memory 18 L18 Read write Unchanged Section 27 3 14 173h LCDBM19 LCD blinking memory 19 L19 Read write Unchanged Section 27 3 14 174h LCDBM20 LCD blinking memory 20 L20 Read write Unchanged Sectio...

Page 1019: ...51 L51 Read write Unchanged Section 27 3 14 194h LCDBM52 LCD blinking memory 52 L52 Read write Unchanged Section 27 3 14 195h LCDBM53 LCD blinking memory 53 L53 Read write Unchanged Section 27 3 14 19...

Page 1020: ...onym Register Name Type Reset Section 1A0h LCDANM0 LCD animation memory 0 T0 Read write Unchanged Section 27 3 15 1A1h LCDANM1 LCD animation memory 1 T1 Read write Unchanged Section 27 3 14 1A2h LCDAN...

Page 1021: ...rw 0 Table 27 8 LCDCTL Register Description Bit Field Type Reset Description 31 18 Reserved R 0h Reserved 17 16 LCDSSEL RW 0h Clock source select for LCD and blinking frequency 00b ACLK 01b VLOCLK 10...

Page 1022: ...mux 110b 7 mux 111b 8 mux 2 LCDSON RW 0h LCD segments on This bit supports flashing LCD applications by turning off all segment lines while leaving the LCD timing generator and R33 enabled 0b All LCD...

Page 1023: ...rs LCDBMx remain unchanged 1b Clear content of all blinking memory registers LCDBMx 17 LCDCLRM RW 0h Clear LCD memory Clears all LCD memory registers LCDMx The bit is automatically reset when the LCD...

Page 1024: ...ency fBLINK is calculated as fBLINK fACLK VLOCLK REFOCLK LFXTCLK LCDBLKDIVx 1 29 LCDBLKPREx NOTE Should only be changed while LCDBLKMODx 00 000b Divide by 512 001b Divide by 1024 010b Divide by 2048 0...

Page 1025: ...e on external Rx3 pins This bit selects the external connections for voltages V2 to V4 with internal bias generation LCDEXTBIAS 0 The bit is don t care if external biasing is selected LCDEXTBIAS 1 NOT...

Page 1026: ...s are port functions 1b Pins are LCD functions 30 LCDS30 RW 0h LCD pin 30 enable This bit affects only pins with multiplexed functions Dedicated LCD pins are always LCD function NOTE Change LCDS30 onl...

Page 1027: ...S21 RW 0h LCD pin 21 enable This bit affects only pins with multiplexed functions Dedicated LCD pins are always LCD function NOTE Change LCDS21 only when LCDON 0 0b Multiplexed pins are port functions...

Page 1028: ...s 11 LCDS11 RW 0h LCD pin 11 enable This bit affects only pins with multiplexed functions Dedicated LCD pins are always LCD function NOTE Change LCDS11 only when LCDON 0 0b Multiplexed pins are port f...

Page 1029: ...RW 0h LCD pin 3 enable This bit affects only pins with multiplexed functions Dedicated LCD pins are always LCD function NOTE Change LCDS3 only when LCDON 0 0b Multiplexed pins are port functions 1b Pi...

Page 1030: ...lways LCD function NOTE Change LCDS63 only when LCDON 0 0b Multiplexed pins are port functions 1b Pins are LCD functions 30 LCDS62 RW 0h LCD pin 62 enable This bit affects only pins with multiplexed f...

Page 1031: ...unction NOTE Change LCDS53 only when LCDON 0 0b Multiplexed pins are port functions 1b Pins are LCD functions 20 LCDS52 RW 0h LCD pin 52 enable This bit affects only pins with multiplexed functions De...

Page 1032: ...D function NOTE Change LCDS42 only when LCDON 0 0b Multiplexed pins are port functions 1b Pins are LCD functions 9 LCDS41 RW 0h LCD pin 41 enable This bit affects only pins with multiplexed functions...

Page 1033: ...S34 RW 0h LCD pin 34 enable This bit affects only pins with multiplexed functions Dedicated LCD pins are always LCD function NOTE Change LCDS34 only when LCDON 0 0b Multiplexed pins are port functions...

Page 1034: ...scription 31 LCDCSS31 RW 0h Selects pin L31 as either common or segment line 0b Segment line 1b Common line 30 LCDCSS30 RW 0h Selects pin L30 as either common or segment line 0b Segment line 1b Common...

Page 1035: ...14 RW 0h Selects pin L14 as either common or segment line 0b Segment line 1b Common line 13 LCDCSS13 RW 0h Selects pin L13 as either common or segment line 0b Segment line 1b Common line 12 LCDCSS12 R...

Page 1036: ...ued Bit Field Type Reset Description 3 LCDCSS3 RW 0h Selects pin L3 as either common or segment line 0b Segment line 1b Common line 2 LCDCSS2 RW 0h Selects pin L2 as either common or segment line 0b S...

Page 1037: ...CDCSS33 LCDCSS32 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 Table 27 14 LCDCSSEL1 Register Description Bit Field Type Reset Description 31 LCDCSS63 RW 0h Selects pin L63 as either common or segment line...

Page 1038: ...0h Selects pin L47 as either common or segment line 0b Segment line 1b Common line 14 LCDCSS46 RW 0h Selects pin L46 as either common or segment line 0b Segment line 1b Common line 13 LCDCSS45 RW 0h S...

Page 1039: ...h Selects pin L36 as either common or segment line 0b Segment line 1b Common line 3 LCDCSS35 RW 0h Selects pin L35 as either common or segment line 0b Segment line 1b Common line 2 LCDCSS34 RW 0h Sele...

Page 1040: ...lculated as fANM fACLK VLO REFO LFXT LCDANMDIVx 1 29 LCDANMPREx NOTE Should only be changed while LCDANMEN 0 000b Divide by 1 001b Divide by 2 010b Divide by 3 011b Divide by 4 100b Divide by 5 101b D...

Page 1041: ...MCTL Register Description continued Bit Field Type Reset Description 3 1 LCDANMSTP RW 0h Determines number of animation frames to be repeated based on value NOTE Should only be changed while LCDANMEN...

Page 1042: ...DBLKOFFIE Reserved r0 r0 r0 r0 rw 0 rw 0 rw 0 r0 Table 27 16 LCDIE Register Description Bit Field Type Reset Description 31 10 Reserved R 0h Reserved 9 LCDANMLOOPIE R W 0h LCD Animation loop interrupt...

Page 1043: ...r0 Table 27 17 LCDIFG Register Description Bit Field Type Reset Description 31 10 Reserved R 0h Reserved 9 LCDANMLOOPIFG R 0h LCD Animation loop interrupt flag 0b No interrupt pending 1b Interrupt due...

Page 1044: ...RMIF G SETLCDBLKO NIFG SETLCDBLKO FFIFG Reserved w1 w1 w1 w1 w1 w1 w1 w1 Table 27 18 LCDSETIFG Register Description Bit Field Type Reset Description 31 10 Reserved W 0h Reserved 9 SETLCDANMLOOPIFG W 0...

Page 1045: ...eserved CLRLCDFRMIF G CLRLCDBLKO NIFG CLRLCDBLKO FFIFG Reserved w1 w1 w1 w1 w1 w1 w1 w1 Table 27 19 LCDCLRIFG Register Description Bit Field Type Reset Description 31 10 Reserved W 0h Reserved 9 CLRLC...

Page 1046: ...cted as segment line LCDCSS index 0b 0b LCD segment off 1b LCD segment on If LCD pin L index is selected as common line LCDCSS index 1b 0b Pin L index not used as COM5 1b Pin L index is used as COM5 4...

Page 1047: ...ted LCD_F Controller Table 27 20 LCDM index Register Description continued Bit Field Type Reset Description 0 MBIT0 RW NA If LCD pin L index is selected as segment line LCDCSS index 0b 0b LCD segment...

Page 1048: ...COM6 1b Pin L index is used as COM6 For full description of the bit in LCD blinking modes refer to LCD Blinking section 5 MBIT5 RW NA If LCD pin L index is selected as segment line LCDCSS index 0b 0b...

Page 1049: ...er to LCD Blinking section 1 MBIT1 RW NA If LCD pin L index is selected as segment line LCDCSS index 0b 0b LCD segment off if blink memory is selected for display 1b LCD segment on if blink memory is...

Page 1050: ...b LCD animation segment off 1b LCD animation segment on The mapping of animation segment to the actual LCD segment is dependent on the mux mode Refer to Animation section for details 4 MBIT4 RW NA If...

Page 1051: ...Table 27 22 LCDANM index Register Description continued Bit Field Type Reset Description 0 MBIT0 RW NA If Animation is enabled LCDANMEN 1 when the animation frame number matches index 0b LCD animation...

Page 1052: ...e first paragraph of Section 4 8 4 1 Execution of IP Protected Secure Zone code 275 Updated the first paragraph in Section 5 8 4 IP Protection Through Secure Memory Zones 317 Updated the first paragra...

Page 1053: ...e resources are subject to change without notice TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource Other reprod...

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