DMA Registers
661
SLAU356I – March 2015 – Revised June 2019
Copyright © 2015–2019, Texas Instruments Incorporated
DMA
11.3.11 DMA_CTLBASE Register (offset = 1008h) [reset = 0h]
DMA Channel Control Data Base Pointer Register. The DMA_CTLBASE Register is a read/write register.
You must configure this register so that the base pointer points to a location in your system memory.
Note: The controller provides no internal memory for storing the channel control data structure.
The amount of system memory that you must assign to the controller depends on the number of DMA
channels and whether you configure it to use the alternate data structure. Therefore, the base pointer
address requires a variable number of bits that depend on the system implementation.
You cannot read this register when the controller is in the reset state.
Figure 11-21. DMA_CTLBASE Register
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
ADDR
rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
ADDR
RESERVED
rw
r-0
Table 11-25. DMA_CTLBASE Register Field Descriptions
Bit
Field
Type
Reset
Description
31-5
ADDR
RW
X
Pointer to the base address of the primary data structure.
4-0
RESERVED
R
0h
Reserved