Programming Model
57
SLAU356I – March 2015 – Revised June 2019
Copyright © 2015–2019, Texas Instruments Incorporated
Cortex-M4F Processor
Register 10: Cortex General-Purpose Register 10 (R10)
Register 11: Cortex General-Purpose Register 11 (R11)
Register 12: Cortex General-Purpose Register 12 (R12)
The Rn (R0 to R12) registers are 32-bit general-purpose registers for data operations and can be
accessed from either privileged or unprivileged mode. They have no special architecturally defined uses.
Most instructions that can specify a general-purpose register can specify R0 to R12.
Low Registers
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Registers R0 to R7 are accessible by all instructions that specify a general-purpose register.
High Registers
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Registers R8 to R12 are accessible by all 32-bit instructions that specify a general-purpose register.
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Registers R8 to R12 are not accessible by any 16-bit instructions.
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Registers R13, R14, and R15 have the following special functions.
1.3.4.2
Register 13: Stack Pointer (SP, R13)
The Stack Pointer (SP) is register R13. In Thread mode, the function of this register changes depending
on the ASP bit in the Control Register (CONTROL) register. When the ASP bit is clear, this register is the
Main Stack Pointer (MSP). When the ASP bit is set, this register is the Process Stack Pointer (PSP). On
reset, the ASP bit is clear, and the processor loads the MSP with the value from address 0x0000.0000.
The MSP can only be accessed in privileged mode; the PSP can be accessed in either privileged or
unprivileged mode.
1.3.4.3
Register 14: Link Register (LR, R14)
•
The Link Register (LR) is register R14, and it stores the return information for subroutines, function
calls, and exceptions. The Link Register can be accessed from either privileged or unprivileged mode.
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The LR receives the return address from PC when a Branch and Link (BL) or Branch and Link with
Exchange (BLX) instruction is executed.
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The LR is also used for exception return. EXC_RETURN is loaded into the LR on exception entry. See
for the values and description.
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At all other times, R14 can be treated as a general-purpose register.
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On reset, the LR has the value 0xFFFF.FFFF
1.3.4.4
Register 15: Program Counter (PC, R15)
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The Program Counter (PC) is register R15, and it contains the address of the next instruction to be
executed.
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On reset, the processor loads the PC with the value of the reset vector, which is at address
0x0000.0004.
•
Bit 0 of the reset vector is loaded into the THUMB bit of the EPSR at reset and must be 1.
•
The PC register can be accessed in either privileged or unprivileged mode.
1.3.4.5
Register 16 Program Status Register (PSR)
This register is also referred to as xPSR.
The Program Status Register (PSR) has three functions, and the register bits are assigned to the different
functions:
•
Application Program Status Register (APSR), bits 31:27, bits 19:16
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Execution Program Status Register (EPSR), bits 26:24, 15:10
•
Interrupt Program Status Register (IPSR), bits 7:0
The PSR IPSR, and EPSR registers can only be accessed in privileged mode; the APSR register can be
accessed in either privileged or unprivileged mode.
