Clock System Operation
381
SLAU356I – March 2015 – Revised June 2019
Copyright © 2015–2019, Texas Instruments Incorporated
Clock System (CS)
6.2
Clock System Operation
After a system reset, the device enters LDO based active mode at core voltage level 0
(AM_LDO_VCORE0). In AM_LDO_VCORE0 mode, the CS module default configuration is:
•
LFXT crystal operation is selected as the clock resource for LFXTCLK
•
LFXTCLK is selected for ACLK (SELAx = 0) and ACLK is undivided (DIVAx = 0)
•
LFXTCLK is selected for BCLK (SELB = 0)
•
LFXT remains disabled. The crystal pins (LFXIN, LFXOUT) are shared with general-purpose I/Os.
LFXIN and LFXOUT pins are set to general-purpose I/Os and LFXT remains disabled until the I/O
ports are configured for LFXT operation. To enable LFXT, the PSEL bits associated with the crystal
pins must be set. When a 32768-Hz crystal is used for LFXTCLK and a crystal fault is detected, the
fault control logic immediately causes ACLK and BCLK to be sourced by REFOCLK (see
•
HFXIN and HFXOUT pins are set to general-purpose I/Os and HFXT is disabled.
•
DCOCLK is selected for MCLK, HSMCLK, and SMCLK (SELMx = SELSx = 3) and each system clock
is undivided (DIVMx = DIVSx = DIVHSx = 0).
The clock system can be configured or reconfigured by software at any time during program execution. All
clock system registers are password protected to prevent inadvertent access except Status register
(CSSTAT) and Interrupt Flag register (CSIFG).
6.2.1 CS Module Features for Low-Power Applications
Conflicting requirements typically exist in low-power applications:
•
Low clock frequency for energy conservation and time keeping
•
High clock frequency for fast response times and fast burst processing capabilities
•
Clock stability over operating temperature and supply voltage
•
Low-cost applications with less constrained clock accuracy requirements; for example, crystal-less
operation
The CS module addresses these conflicting requirements by allowing the user to select from the five
available system clock signals: ACLK, MCLK, HSMCLK, SMCLK, and BCLK. Several clock resources are
available to these system clocks. A flexible clock distribution and divider system is provided to fine tune
the individual clock requirements.
6.2.2 LFXT Oscillator
The LFXT oscillator supports ultra-low-current consumption using a 32768-Hz watch crystal. A watch
crystal connects to LFXIN and LFXOUT and requires external capacitors on both terminals. These
capacitors should be sized according to the crystal or resonator specifications. Different crystals or
resonators are supported by LFXT by choosing the proper LFXTDRIVE settings.
The LFXT pins are shared with general-purpose I/O ports. At power up, the default operation is LFXT
crystal operation. However, LFXT remains disabled until the ports shared with LFXT are configured for
LFXT operation. The configuration of the shared I/O is determined by the PSEL bit associated with LFXIN
and the LFXTBYPASS bit. Setting the PSEL bit causes the LFXIN and LFXOUT ports to be configured for
LFXT operation. If LFXTBYPASS is also set, LFXT is configured for bypass mode of operation, and the
oscillator associated with LFXT is powered down. In bypass mode of operation, LFXIN can accept an
external square-wave clock input signal and LFXOUT is configured as a general-purpose I/O. The PSEL
bit associated with LFXOUT is a don't care.
If the PSEL bit associated with LFXIN is cleared, both LFXIN and LFXOUT ports are configured as
general-purpose I/Os, and LFXT is disabled.
LFXT is enabled under any of the following conditions:
•
For any active mode or LPM0 mode
–
LFXT_EN = 1
–
LFXT is a source for ACLK (SELAx = 0).
