Texas Instruments SimpleLink MSP432P4 Series, Technical Reference Manual

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Instruction Set Summary
75 SLAU356I – March 2015 – Revised June 2019
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Copyright © 2015–2019, Texas Instruments Incorporated
Cortex-M4F Processor
1.8 Instruction Set Summary
The processor implements a version of the Thumb instruction set. Table 1-12 lists the supported
instructions.
NOTE: In Table 1-12 :
• Angle brackets, <>, enclose alternative forms of the operand
• Braces, {}, enclose optional operands
• The Operands column is not exhaustive
• Op2 is a flexible second operand that can be either a register or a constant
• Most instructions can use an optional condition code suffix
For more information on the instructions and operands, see the instruction descriptions in the
Arm® Cortex-M4 Technical Reference Manual .
Table 1-12. Cortex-M4F Instruction Summary
Mnemonic Operands Brief Description Flags
ADC, ADCS {Rd,} Rn, Op2 Add with Carry N, Z, C, V
ADD, ADDS {Rd,} Rn, Op2 Add N, Z, C, V
ADD, ADDW {Rd,} Rn, #imm12 Add –
ADR Rd, label Load PC-relative Address –
AND, ANDS {Rd,} Rn, Op2 Logical AND N, Z, C
ASR, ASRS Rd, Rm, <Rs|#n> Arithmetic Shift Right N, Z, C
B label Branch –
BFC Rd, #lsb, #width Bit Field Clear –
BFI Rd, Rn, #lsb, #width Bit Field Insert –
BIC, BICS {Rd,} Rn, Op2 Bit Clear N, Z, C
BKPT #imm Breakpoint –
BL label Branch with Link –
BLX Rm Branch indirect with Link –
BX Rm Branch indirect –
CBNZ Rn, label Compare and Branch if Non Zero –
CBZ Rn, label Compare and Branch if Zero –
CLREX – Clear Exclusive –
CLZ Rd, Rm Count Leading Zeros –
CMN Rn, Op2 Compare Negative N, Z, C, V
CMP Rn, Op2 Compare N, Z, C, V
CPSID i Change Processor State, Disable Interrupts –
CPSIE i Change Processor State, Enable Interrupts –
DMB – Data Memory Barrier –
DSB – Data Synchronization Barrier –
EOR, EORS {Rd,} Rn, Op2 Exclusive OR N, Z, C
ISB – Instruction Synchronization Barrier –
IT – If-Then condition block –
LDM Rn{!}, reglist Load Multiple registers, increment after –
LDMDB, LDMEA Rn{!}, reglist Load Multiple registers, decrement before –
LDMFD, LDMIA Rn{!}, reglist Load Multiple registers, increment after –
LDR Rt, [Rn, #offset] Load Register with word –
LDRB, LDRBT Rt, [Rn, #offset] Load Register with byte –
LDRD Rt, Rt2, [Rn, #offset] Load Register with two bytes –
LDREX Rt, [Rn, #offset] Load Register Exclusive –