Introduction
52
SLAU356I – March 2015 – Revised June 2019
Copyright © 2015–2019, Texas Instruments Incorporated
Cortex-M4F Processor
Table 1-1. Cortex-M4F Optional Parameters Configuration in MSP432P4xx (continued)
SL NO
Configuration
Feature
Cortex M4 Options
MSP432P4xx Configuration
12
Trace support level
No Trace, Standard Trace, Full Trace, Full
Trace plus HTM port
Standard trace: ITM, TPIU and DWT triggers
and counters present. ETM and HTM are not
present.
This chapter provides information on the implementation of the Cortex-M4F processor, including the
programming model, the memory model, the exception model and fault handling.
For technical details on the instruction set, see the Cortex-M4 instruction set chapter in the
.
1.1.1 Block Diagram
The Cortex-M4F processor is built on a high-performance processor core with a 3-stage pipeline Harvard
architecture, making it ideal for demanding embedded applications. The processor delivers exceptional
power efficiency through an efficient instruction set and extensively optimized design, providing high-end
processing hardware including IEEE754-compliant single-precision floating-point computation, a range of
single-cycle and SIMD multiplication and multiply-with-accumulate capabilities, saturating arithmetic and
dedicated hardware division.
To facilitate the design of cost-sensitive devices, the Cortex-M4F processor implements tightly coupled
system components that reduce processor area while significantly improving interrupt handling and system
debug capabilities. The Cortex-M4F processor implements a version of the Thumb® instruction set based
on Thumb-2 technology, ensuring high code density and reduced program memory requirements. The
Cortex-M4F instruction set provides the exceptional performance expected of a modern 32-bit
architecture, with the high code density of 8-bit and 16-bit microcontrollers.
The Cortex-M4F processor closely integrates a nested interrupt controller (NVIC), to deliver industry-
leading interrupt performance. The MSP432P4xx NVIC includes a nonmaskable interrupt (NMI) and
provides eight interrupt priority levels. The tight integration of the processor core and NVIC provides fast
execution of interrupt service routines (ISRs), dramatically reducing interrupt latency. The hardware
stacking of registers and the ability to suspend load-multiple and store-multiple operations further reduce
interrupt latency. Interrupt handlers do not require any assembler stubs, which removes code overhead
from the ISRs. Tail-chaining optimization also significantly reduces the overhead when switching from one
ISR to another. To optimize low-power designs, the NVIC integrates with the sleep modes, including
Deep-sleep mode, which enables the entire device to be rapidly powered down.
shows the CPU block diagram.
