Debug Peripherals Registers
194
SLAU356I – March 2015 – Revised June 2019
Copyright © 2015–2019, Texas Instruments Incorporated
Cortex-M4F Peripherals
2.5.2.2
CYCCNT Register (Offset = 4h) [reset = 00000000h]
CYCCNT is shown in
and described in
.
DWT Current PC Sampler Cycle Count Register. Use the DWT Current PC Sampler Cycle Count Register
to count the number of core cycles. This count can measure elapsed execution time. This is a free-running
counter. The counter has three functions: (1) When PCSAMPLENA is set, the PC is sampled and emitted
when the selected tapped bit changes value (0 to 1 or 1 to 0) and any post-scalar value counts to 0. (2)
When CYCEVTENA is set (and PCSAMPLENA is clear), an event is emitted when the selected tapped bit
changes value (0 to 1 or 1 to 0) and any post-scalar value counts to 0. (3) Applications and debuggers
can use the counter to measure elapsed execution time. By subtracting a start and an end time, an
application can measure time between in-core clocks (other than when Halted in debug). This is valid to
2
32
core clock cycles (for example, almost 86 seconds at 50MHz).
Figure 2-98. CYCCNT Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
CYCCNT
rw-(0)
Table 2-110. CYCCNT Register Field Descriptions
Bit
Field
Type
Reset
Description
31-0
CYCCNT
R/W
0h
Current PC Sampler Cycle Counter count value. When enabled, this
counter counts the number of core cycles, except when the core is
halted. CYCCNT is a free running counter, counting upwards. It
wraps around to 0 on overflow. The debugger must initialize this to 0
when first enabling.
