DMA Introduction
623
SLAU356I – March 2015 – Revised June 2019
Copyright © 2015–2019, Texas Instruments Incorporated
DMA
11.1 DMA Introduction
MSP432P4xx DMA is built around the Arm PL230 microDMA controller (µDMAC) (see
). The
µDMAC is an Advanced Microcontroller Bus Architecture (AMBA) compliant System-on-Chip (SoC)
peripheral that is developed, tested, and licensed by Arm.
The principal features are:
•
Compatible with AHB-Lite for the DMA transfers
•
Compatible with APB for programming the registers
•
Single AHB-Lite master for transferring data using a 32-bit address bus and 32-bit data bus
•
Multiple independent DMA channels (number of DMA channels is device specific)
•
Each DMA channel has dedicated handshake signals.
•
Each DMA channel has a programmable priority level.
•
Multiple channels with same priority level are arbitrated using a fixed priority that is determined by the
DMA channel number.
•
Supports multiple transfer types:
–
Memory-to-memory transfers
–
Memory-to-peripheral transfers
–
Peripheral-to-memory transfers
•
Supports multiple DMA cycle types
•
Supports multiple DMA transfer data widths
•
Each DMA channel can access a primary and an alternate channel control data structure.
•
All of the channel control data is stored in system memory in little-endian format.
•
Performs all DMA transfers using the SINGLE AHB-Lite burst type
•
Destination data width is equal to the source data width.
•
Number of transfers in a single DMA cycle can be programmed from 1 to 1024.
•
Transfer address increment can be greater than the data width.
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Single output to indicate when an ERROR condition occurs on the AHB bus
•
Automatic low-power mode entry when not in use
•
Triggers for each channel can be selected by the user.
•
Software trigger support for each channel
•
Raw and masked interrupts for optimal interrupt processing
