Exception Model
70
SLAU356I – March 2015 – Revised June 2019
Copyright © 2015–2019, Texas Instruments Incorporated
Cortex-M4F Processor
1.5.8 Exception Entry and Return
The processor implements advanced exception and interrupt handling, as described in the
).
To reduce interrupt latency, the processor implements both interrupt late-arrival and interrupt tail-chaining
mechanisms:
•
There is a maximum of twelve cycle latency from asserting the interrupt to execution of the first
instruction of the ISR when the memory being accessed has no wait states being applied. The first
instruction to be executed is fetched in parallel to the stack push.
•
Returns from interrupts takes twelve cycles where the instruction being returned to is fetched in parallel
to the stack pop.
•
Tail chaining requires six cycles when using zero wait state memory. No stack pushes or pops are
performed and only the instruction for the next ISR is fetched.
To minimize interrupt latency, the processor abandons any divide instruction to take any pending interrupt.
On return from the interrupt handler, the processor restarts the divide instruction from the beginning. The
processor implements the Interruptible-Continuable Instruction field. Load multiple (LDM) operations and
store multiple (STM) operations are interruptible. The EPSR holds the information required to continue the
load or store multiple from the point where the interrupt occurred.
Descriptions of exception handling use the following terms:
•
Preemption: When the processor is executing an exception handler, an exception can preempt the
exception handler if its priority is higher than the priority of the exception being handled. See
for more information about preemption by an interrupt. When one exception preempts
another, the exceptions are called nested exceptions. See
for more information.
•
Return: Return occurs when the exception handler is completed, and there is no pending exception
with sufficient priority to be serviced and the completed exception handler was not handling a late-
arriving exception. The processor pops the stack and restores the processor state to the state it had
before the interrupt occurred. See
for more information.
•
Tail-Chaining: This mechanism speeds up exception servicing. On completion of an exception handler,
if there is a pending exception that meets the requirements for exception entry, the stack pop is
skipped and control transfers to the new exception handler.
•
Late-Arriving: This mechanism speeds up preemption. If a higher priority exception occurs during state
saving for a previous exception, the processor switches to handle the higher priority exception and
initiates the vector fetch for that exception. State saving is not affected by late arrival because the state
saved is the same for both exceptions. Therefore, the state saving continues uninterrupted. The
processor can accept a late arriving exception until the first instruction of the exception handler of the
original exception enters the execute stage of the processor. On return from the exception handler of
the late-arriving exception, the normal tail-chaining rules apply.
1.5.8.1
Exception Entry
Exception entry occurs when there is a pending exception with sufficient priority and either the processor
is in Thread mode or the new exception is of higher priority than the exception being handled, in which
case the new exception preempts the original exception. When one exception preempts another, the
exceptions are nested.
Sufficient priority means the exception has more priority than any limits set by the mask registers (see the
PRIMASK, FAULTMASK, and BASEPRI registers). An exception with less priority than this is pending but
is not handled by the processor.
When the processor takes an exception, unless the exception is a tail-chained or a late-arriving exception,
the processor pushes information onto the current stack. This operation is referred to as
stacking
and the
structure of eight data words is referred to as
stack frame
.
When using floating-point routines, the Cortex-M4F processor automatically stacks the architected
floating-point state on exception entry.
shows the Cortex-M4F stack frame layout when floating-
point state is preserved on the stack as the result of an interrupt or an exception.
