Functional Peripherals Description
84
SLAU356I – March 2015 – Revised June 2019
Copyright © 2015–2019, Texas Instruments Incorporated
Cortex-M4F Peripherals
2.2.4 Memory Protection Unit (MPU)
This section describes the Memory protection unit (MPU). The MPU divides the memory map into a
number of regions and defines the location, size, access permissions, and memory attributes of each
region. The MPU supports independent attribute settings for each region, overlapping regions, and export
of memory attributes to the system.
The MPU provides full support for:
•
Protection regions – eight distinct regions are supported
•
Overlapping protection regions, with ascending region priority
–
7 = highest priority
–
0 = lowest priority
•
Access permissions
•
Exporting memory attributes to the system
MPU mismatches and permission violations invoke the programmable-priority MemManage fault handler.
See the
Armv7-M Architecture Reference Manual
) for more information.
You can use the MPU to:
•
enforce privilege rules
•
separate processes
•
enforce access rules
The MPU registers are listed in
The access permission bits TEX, C, B, AP, and XN, of the Region Access Control Register controls
access to the corresponding memory region. (See
for more information on access
permission bits). If an access is made to an area of memory without the required permissions, a
permission fault is raised. If MemManage fault is enabled in the system, then it interrupts the processor as
MemManage fault else it escalates itself as Hard Fault to interrupt the processor.
Each memory region of size above 256 bytes can be divided into 8 sub-regions of equal size and each of
these sub-regions can be selectively disabled for protection via MPU.
When memory regions overlap, a memory access is affected by the attributes of the region with the
highest number. For example, the attributes for region 7 take precedence over the attributes of any region
that overlaps region 7.
The background region has the same memory access attributes as the default memory map, but is
accessible from privileged software only.
The Cortex-M4 MPU memory map is unified, meaning that instruction accesses and data accesses have
the same region settings.
If a program accesses a memory location that is prohibited by the MPU, the processor generates a
memory management fault, causing a fault exception and possibly causing termination of the process in
an OS environment. In an OS environment, the kernel can update the MPU region setting dynamically
based on the process to be executed. Typically, an embedded OS uses the MPU for memory protection.
Configuration of MPU regions is based on memory types (see
for more information on
memory type definition ).
See
for guidelines for programming the access permission bits of MPU in MSP432P4xx
devices.
To avoid unexpected behavior, disable the interrupts before updating the attributes of a region that the
interrupt handlers might access.
Ensure software uses aligned accesses of the correct size to access MPU registers:
•
Except for the MPU Region Attribute and Size Register (RASR), all MPU registers must be accessed
with aligned word accesses.
•
The RASR register can be accessed with byte or aligned halfword or word accesses. The processor
does not support unaligned accesses to MPU registers.
