Clock System Operation
391
SLAU356I – March 2015 – Revised June 2019
Copyright © 2015–2019, Texas Instruments Incorporated
Clock System (CS)
NOTE:
Fault conditions
LFXT_OscFault:
This signal is set after the LFXT oscillator has stopped operation and is
cleared after operation resumes. The fault condition causes LFXTIFG to be set and remain
set. If the user clears LFXTIFG and the fault condition still exists, LFXTIFG is set again.
HFXT_OscFault:
This signal is set after the HFXT oscillator has stopped operation and is
cleared after operation resumes. The fault condition causes HFXTIFG to be set and remain
set. If the user clears HFXTIFG and the fault condition still exists, HFXTIFG is set again.
DCOR_Open_OscFault:
This signal is set upon DCO external resistor open circuit fault. The
fault condition causes DCOR_OPNIFG to be set and remain set. If the user clears
DCOR_OPNIFG and the fault condition still exists, DCOR_OPNIFG is set again.
DCOR_Short_OscFault:
This signal is set upon DCO external resistor short circuit fault. The
fault condition causes DCOR_SHTIFG to be set and leads to device POR. DCO_SHTIFG is
cleared upon device power cycle or by writing into CLR bit of RSTCTL_CSRESET_CLR
register.
NOTE:
Fault logic
As long as a fault condition still exists, the individual fault flags remains set. The clock logic
switches back to the original user settings before the fault condition when the fault condition
is resolved and the corresponding fault flag is cleared.
6.2.11 Start-up Counters
The LFXT includes a counter that makes sure that a programmable number of clock cycles have passed
before the LFXT_OscFault signal is cleared. The counter can be programmed from 4096 to 32768 counts
using the FCNTLF bits. The default is the maximum count. Any crystal fault restarts the counter. It is also
possible to restart the counter directly through software by setting the RCNTLF bit. The RCNTLF bit is
self-clearing. When it is written, the counter immediately restarts its count. For applications that do not
require the start-up counter, it can be disabled by clearing FCNTLF_EN. Clearing FCNTLF_EN
immediately clears and halts the timer. Disabling the counters does not disable the fault logic. The counter
is available in both normal and bypass modes of operation.
Similarly, HFXT includes a counter that makes sure that a programmable number of clock cycles have
passed before the HFXT_OscFault signal is cleared. The counter can be programmed from 2048 to 16384
counts using the FCNTHF bits. The default is the maximum count. Any crystal fault restarts the counter. It
is also possible to restart the counter directly through software by setting RCNTHF. RCNTHF bit is self-
clearing. Once written, the counter immediately restarts its count. For applications that do not require the
start-up counter, it can be disabled by clearing FCNTHF_EN. Clearing FCNTHF_EN immediately clears
and halts the timer. Disabling the counters does not disable the fault logic. The counter is available in both
normal and bypass modes of operation.
6.2.12 Synchronization of Clock Signals
When switching ACLK, MCLK, HSMCLK, or SMCLK from one clock source to the another, the switch is
synchronized to avoid critical race conditions (see
).
•
The current clock cycle continues until the next rising edge.
•
The clock remains high until the next rising edge of the new clock.
•
The new clock source is selected and continues with a full high period.
