Texas Instruments SimpleLink MSP432P4 Series, Technical Reference Manual

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Cortex-M4F Peripherals Introduction
81 SLAU356I – March 2015 – Revised June 2019
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Copyright © 2015–2019, Texas Instruments Incorporated
Cortex-M4F Peripherals
2.1 Cortex-M4F Peripherals Introduction
The following peripherals are described in this chapter:
• SysTick (see Section 2.2.1 )
Provides a simple, 24-bit clear-on-write, decrementing, wrap-on-zero counter with a flexible control
mechanism.
• Nested Vectored Interrupt Controller (NVIC) (see Section 2.2.2 )
– Facilitates low-latency exception and interrupt handling
– Controls power management
– Implements system control registers
• System Control Block (SCB) (see Section 2.2.3 )
Provides system implementation information and system control, including configuration, control, and
reporting of system exceptions.
• Memory Protection Unit (MPU) (see Section 2.2.4 )
Supports the standard Armv7 Protected Memory System Architecture (PMSA) model. The MPU
provides full support for protection regions, overlapping protection regions, access permissions, and
exporting memory attributes to the system.
• Floating-Point Unit (FPU) (see Section 2.2.5 )
Fully supports single-precision add, subtract, multiply, divide, multiply and accumulate, and square root
operations. It also provides conversions between fixed-point and floating-point data formats, and
floating-point constant instructions.
Table 2-1 shows the address map of the Private Peripheral Bus (PPB). Some peripheral register regions
are split into two address regions, as indicated by two addresses listed.
Table 2-1. Core Peripheral Register Regions
Address Core Peripheral Section
0xE000_E010-0xE000_E01F System Timer Section 2.2.1
0xE000_E100-0xE000_E4EF
0xE000_EF00-0xE000_EF03
Nested Vectored Interrupt Controller Section 2.2.2
0xE000_E008-0xE000_E00F
0xE000_ED00-0xE000_ED3F
System Control Block Section 2.2.3
0xE000_ED90-0xE000_EDB8 Memory Protection Unit Section 2.2.4
0xE000_EF30-0xE000_EF44 Floating Point Unit Section 2.2.5
2.2 Functional Peripherals Description
This chapter describes the implementation of the Cortex-M4 processor functional peripherals: SysTick,
NVIC, SCB, MPU, FPU.
2.2.1 System Timer (SysTick)
Cortex-M4 includes an integrated system timer, SysTick, which provides a simple 24-bit clear-on-write
decrementing wrap-on-zero counter with a flexible control mechanism. The counter can be used in several
different ways, for example:
• An RTOS tick timer that fires at a programmable rate (for example, 100 Hz) and invokes a SysTick
routine.
• A high-speed alarm timer using the system clock.
• A variable rate alarm or signal timer—the duration is range-dependent on the reference clock used and
the dynamic range of the counter.
• A simple counter used to measure time to completion and time used.
• An internal clock source control based on missing/meeting durations. The COUNT bit in the STCSR
control and status register can be used to determine if an action completed within a set duration, as