Hioki Power HiTester 3193, Instruction Manual

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12.3 Interface Outline
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bit 2 bit 1 bit 0
ESB1 ESB1 ESB0
Logical sum
& & & & &
& & &
Status byte register (STB)
Event status enable register 0 - 2 (ESER0 - 2)
Event status register 0 - 2 (ESR0 - 2)
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
・・・ ・・・ ・・・ ・・・ ・・・ ・・・ ・・・
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
NOTE
(3) Event status registers specific to this unit
(ESR0, ESR1, ESR2)
This unit has three event status registers, and three corresponding event
status enable registers.
The event status registers are numbered 0 to 2, and are each 8-bit registers;
they correspond to bits ESB0 to ESB3 of the status byte.
Each bit has a particular 3193 event allocated to it. The constituent bits are
masked by the corresponding event status enable register, then the summary
(logical OR) is copied to one of bits 0 to 2 (ESB0- ESB2) of the status byte
(STB).
Each event status register has a corresponding event status enable register
(mask), and the individual bits in this register can be set by the user, to
mask the events.
The event status registers are cleared in the following three cases:
1. The "*CLS" command is received.
2. The contents are read by a "*ESR0?" to "*"ESR2?" query.
3. When the unit is powered on.
All registers are not backed up by battery.
The data must be set each time the unit is switched on.