122
────────────────────────────────────────────────────
12.3 Interface Outline
────────────────────────────────────────────────────
12.3.13 Event Registers
bit 5
ESB
MA
SRQ
MSS
Logical sum
&
&
&
&
&
&
&
&
Status byte register (STB)
Standard event status enable register (SESER)
Standard event status register (SESR)
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
PON
URQ
CME
EXE
DDE
QYE
RQC
OPC
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
PON
URQ
CME
EXE
DDE
QYE
RQC
OPC
・・・
・・・
・・・
・・・
・・・
・・・
・・・
(1) Standard event status register (SESR)
The standard event status register is an 8-bit register. If any bit in the
standard event status register is set to 1 (after masking by the standard event
status enable register), bit 5 (ESB) of the status byte register is set to 1.
The standard event status register is cleared in the following three situations:
①
When a "*CLS" command is received.
②
When an "*ESR?" query is received.
③
When the unit is powered on.
Summary of Contents for Power HiTester 3193
Page 2: ......
Page 50: ...32 3 9 Operations During Power Failure ...
Page 76: ...58 4 13 Degaussing ...
Page 80: ...62 5 2 Setting the Frequency Range fa ...
Page 108: ...90 9 3 Internal Circuit for the External Control and Timing ...
Page 112: ...94 10 3 Output Rate ...
Page 250: ...232 13 9 Error and Overflow Displays ...
Page 278: ...260 17 5 Internal Block Diagram ...
Page 284: ...266 19 2 Installation Procedures For JIS standard For EIA standard External Dimensions ...
Page 300: ...282 20 4 Internal Block Diagram of the 3193 ...
Page 306: ...INDEX 4 Index ...
Page 307: ......
Page 308: ......
Page 309: ......
Page 310: ......