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4. Operating Instruction
4.2 Advanced operation guide
134
Gated FFT: the way of FFT spectrum measurement if the trigger conditions are satisfied, which is called as
the gated FFT. The FFT spectrum is the input signal spectrum through FFT calculation from a time domain
waveform during collection. The time for collecting the domain waveform is similar to the gate length. The
time for collecting the domain waveform is similar to the gate length. Different from the Sweep Time Gate,
under Gated FFT, the gate length is determined by the currently set resolution bandwidth and cannot be set
and modified through menu. When the Span is less than 10 MHz, in particular for small resolution bandwidth,
the FFT measurement is faster than the Sweep measurement; therefore, for a given signal period, compared
with Gated LO, the Gated FFT gets higher frequency resolution.
4.2.9.3 More about time gate measurement
The example demonstrates how to measure a specific signal by the use of time gate. Most signals which are
required to be measured via the time gate are relatively complex, sometimes even some additional steps are
needed for the measurement.
1)
Be aware of the signals to be measured in time domain and how to synchronize with the trigger
signals
Adjust the gate position by setting the gate delay parameters related to the trigger signals. In order to set the
gate delay parameters, you need to know the temporal relation between the trigger signal and the signal to be
measured. If not, the following parameters of the signal are required to determined by the oscilloscope:
Trigger polarity (positive or negative).
Pulse repetition interval (PRI) refers to the time interval between two trigger events.
Pulse width (τ).
The signal delay (SD) refers to the time interval between the trigger event and stable signal, and the SD
will be 0 if the trigger event and signal appear simultaneously.
Fig. 4.51 Relation of time-domain parameters
In Fig. 4.51, relevant parameters are listed as follows:
Pulse repetition interval (PRI) is 9ms.
Pulse width (τ) is 3ms.
For the trigger of positive edge, the time of signal delay (SD) is 1ms, while for the trigger of negative
edge, the SD is 0.8ms.
Gate delay time (D) is 2.5ms.
Summary of Contents for 4051 Series
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