Ceyear 4051 Series, User Manual

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4. Operating Instruction
4.2 Advanced operation guide
130
4.2.9.2 Measurement principle of time gate
The measurement of time gate refers to the Series Signal Analyzer uses the trigger signals to carry out the
alternative measurement, see Fig. 4.44. The gate width determines the capture time of measurement data (the
signal pass through if gated, and the signal fails to pass through if closed). In proper conditions, the signal
measured by the analyzer merely refers to the input signal during the gating, and other signals will be shielded
if the setting is correct.
The gating conditions are determined by the trigger mechanism of the Series Signal Analyzer, including edge
triggering and level triggering, which are described as follows:
Edge triggering:when the selected edge (positive or negative edge) of the trigger signal arrives, whether the
Gate is ON is determined by the subsequent gate delay and gate length (both can be set by the menu). The
Gate is ON whenever the trigger event arrives and the gate delay time is passed. During the gate length, the
signal passes through; when the gate length ends, the signal is blocked, as shown in Fig. 4.44. In general, for
edge triggering, the trigger signal is an TTL periodic signal, whose positive and negative edges are
synchronous with those of the measured pulse signal. Gate delay time refers to the time during which the
Series Signal Analyzer needs to wait from the trigger event to Gate ON.
Fig. 4.44 Sequence diagram of edge triggering
Level triggering: when the gate signal has achieved a certain level (high level or low level. In Series Signal
Analyzer, positive polarity indicates high level; and negative polarity indicates low level), the signal passes
through; and when the gate signal fails to achieve specified level, the signal is blocked, as shown in Fig. 4.45.
In Level triggering, the Gate Delay and Gate Length parameters are void.
Fig. 4.45 Sequence diagram of level triggering