Ceyear 4051 Series, User Manual

Page: 145 / 751

4. Operating Instruction
4.2 Advanced operation guide
131
The following three parameters are required to be considered when the time gate judges the signal passed or
shielded:
 Triggering conditions: in general, for edge triggering, the trigger signal is a TTL periodic signal, while
the level triggering refer to the high/low electrical level.
 Gate delay: the gate delay time refers to the duration from the time that triggering conditions are satisfied
to gating signal (for the edge triggering).
 Gate width: the gate width determines the time duration of gating signal (for the edge triggering).
Research on the spectrum measurement of double pulse RF signal can better help users to understand the time
gate, where the time allocation of three key signals is required to be considered during the measurement. The
three signals include:
 Measured pulse RF signal
 The time gate trigger signal provided by the signal generator.
 Gate output signal from the BNC connector of the back panel of the Series Signal Analyzer. The signal is
the TTL low electric level when the Gate is ―Off‖ (shielding), and TTL high electric level when ―On‖
(measurement).
Observing the three signals with an oscilloscope, you can be fully aware of the impact of the time allocation
among them. The three signals on the oscilloscope are shown in Fig. 4.46.
The main purpose is to measure the spectrum of pulse sequence 1 and determine whether there is low-level
modulation or false signal. The carrier frequencies of pulse sequence for Signal 1 and Signal 2 are similar, so
both frequency domain spectra are overlapped. But the amplitude of Signal 2 is wider; therefore, its spectrum
of the pulse sequence is stronger. If there is no time gate, it is impossible to observe the pulse sequence of
Signal 1.
The pulse sequence of spectrum is covered by that of Signal 2.
To measure the pulse sequence 1, the time gate must opened in the pulse sequence 1. The tame gate should be
closed in other time periods so that other signals are blocked. The gate delay and width should be set to have
the gate opened only in a certain area of the central pulse as shown in Fig. 4.46 Never position the gate at the
positive or negative edge of the pulse. For the grid line marked ―Gate‖ in the figure, the output signal indicates
the actual position of gate on the time axis if the gate is activated.
Fig. 4.46 Temporal relation between signal and gate
If you complete the gate measurement of Series Signal Analyzer, you will merely observe the spectrum of
pulse train 1 as shown in Fig. 4.47; that of the pulse train 2 has been shielded. Additionally, you have to
eliminate the spectrum generated at the pulse edge during the observation of pulse train 1, that is, the gate
should be placed in the middle position of the pulse.