506
Initialization
Clear TE and RE bits in SCSCR to 0
Set value in SCBRR
Clear FER/ERS, PER
and ORER flags in SCSSR to 0
Wait
Set TIE, RIE, TE, and RE bits
in SCSCR
Has a 1-bit
interval elapsed?
End
(2)
Set parity in O/
E
bit,
set clock in CKS1 and CKS0 bits,
and set C/
A
, in SCSMR
(3)
Set clock in CKE1 and CKE0 bits,
and clear TIE, RIE, TE, RE, MPIE,
and TEIE bits to 0, in SCSCR
(6)
(5)
(4)
(1)
(7)
No
Yes
Set SMIF, SDIR,
and SINV bits in SCSMR
Note: Numbers in parentheses refer to steps in the preceding procedure description.
Figure 15.5 Initialization Flowchart (Example)
Содержание SH7709S
Страница 2: ...Hitachi SuperH RISC engine SH7709S Hardware Manual ADE 602 250 Rev 1 0 09 21 01 Hitachi Ltd ...
Страница 75: ...56 ...
Страница 107: ...88 ...
Страница 125: ...106 ...
Страница 139: ...120 ...
Страница 203: ...184 ...
Страница 245: ...226 ...
Страница 292: ...273 T1 CKIO A25 to A0 CSn RD WR RD D31 to D0 WEn D31 to D0 BS T2 Read Write Figure 10 6 Basic Timing of Basic Interface ...
Страница 323: ...304 Tp TRr TRrw TRrw CKIO CKE CSn RAS3U RAS3L CASU CASL RD WR Figure 10 28 Synchronous DRAM Auto Refresh Timing ...
Страница 411: ...392 ...
Страница 609: ...590 ...
Страница 635: ...616 ...
Страница 663: ...644 ...
Страница 679: ...660 ...