704
CKIO
A12 or A10
RD/
WR
CSn
RAS
CAS
BS
DQMxx
CKE
A25 to A16
A15 to A0
Tp
Tpw
Tr
Trw
Tc1
Tc2
Tc3
D31 to
D0
t
AD
t
AD
t
CSD3
t
CSD3
t
RWD
t
RWD
t
RWD
t
RWD
t
RASD2
t
RASD2
t
RASD2
t
RASD2
t
DQMD
t
DQMD
t
DQMD
t
WDD2
t
WDD2
t
BSD
t
BSD
(High)
t
AD
t
AD
t
AD
t
AD
t
AD
t
AD
Td4
Write command
Column address
t
CASD2
t
CASD2
Row
address
Row
address
t
AD
t
AD
Row address
tDAKD1
tDAKD1
DACKn
Figure 23.36 Synchronous DRAM Burst Write Bus Cycle
(RAS Down, Different Row Address, TPC = 1, RCD = 1)
Содержание SH7709S
Страница 2: ...Hitachi SuperH RISC engine SH7709S Hardware Manual ADE 602 250 Rev 1 0 09 21 01 Hitachi Ltd ...
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Страница 292: ...273 T1 CKIO A25 to A0 CSn RD WR RD D31 to D0 WEn D31 to D0 BS T2 Read Write Figure 10 6 Basic Timing of Basic Interface ...
Страница 323: ...304 Tp TRr TRrw TRrw CKIO CKE CSn RAS3U RAS3L CASU CASL RD WR Figure 10 28 Synchronous DRAM Auto Refresh Timing ...
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