212
output of the chip’s CKIO pin. Consequently, if a large number of ICs are operating on the clock
cycle, the CKIO pin load will be large. This mode, however, assumes a comparatively large-scale
system. If a large number of ICs are operating on the clock cycle, a clock generator with a number
of low-skew clock outputs can be provided, so that the ICs can operate synchronously by
distributing the clocks to each one.
As PLL circuit 1 compensates for fluctuations in the CKIO pin load, this mode is suitable for
connection of synchronous DRAM.
Table 9.4
Available Combinations of Clock Mode and FRQCR Values
Clock
Mode
FRQCR
PLL1
PLL2
Clock Rate
*
(I:B:P)
Input Frequency
Range
CKIO Frequency
Range
0
H'0100
ON (
×
1) ON (
×
1) 1:1:1
25 MHz to 33.34 MHz
25 MHz to 33.34 MHz
H'0101
ON (
×
1) ON (
×
1) 1:1:1/2
25 MHz to 66.67 MHz
25 MHz to 66.67 MHz
H'0102
ON (
×
1) ON (
×
1) 1:1:1/4
25 MHz to 66.67 MHz
25 MHz to 66.67 MHz
H'0111
ON (
×
2) ON (
×
1) 2:1:1
25 MHz to 33.34 MHz
25 MHz to 33.34 MHz
H'0112
ON (
×
2) ON (
×
1) 2:1:1/2
25 MHz to 66.67 MHz
25 MHz to 66.67 MHz
H'0115
ON (
×
2) ON (
×
1) 1:1:1
25 MHz to 33.34 MHz
25 MHz to 33.34 MHz
H'0116
ON (
×
2) ON (
×
1) 1:1:1/2
25 MHz to 66.67 MHz
25 MHz to 66.67 MHz
H'0122
ON (
×
4) ON (
×
1) 4:1:1
25 MHz to 33.34 MHz
25 MHz to 33.34 MHz
H'0126
ON (
×
4) ON (
×
1) 2:1:1
25 MHz to 33.34 MHz
25 MHz to 33.34 MHz
H'012A
ON (
×
4) ON (
×
1) 1:1:1
25 MHz to 33.34 MHz
25 MHz to 33.34 MHz
H'A100
ON (
×
3) ON (
×
1) 3:1:1
25 MHz to 33.34 MHz
25 MHz to 33.34 MHz
H'A101
ON (
×
3) ON (
×
1) 3:1:1/2
25 MHz to 66.67 MHz
25 MHz to 66.67 MHz
H'E100
ON (
×
3) ON (
×
1) 1:1:1
25 MHz to 33.34 MHz
25 MHz to 33.34 MHz
H'E101
ON (
×
3) ON (
×
1) 1:1:1/2
25 MHz to 66.67 MHz
25 MHz to 66.67 MHz
H'A111
ON (
×
6) ON (
×
1) 6:1:1
25 MHz to 33.34 MHz
25 MHz to 33.34 MHz
Содержание SH7709S
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Страница 292: ...273 T1 CKIO A25 to A0 CSn RD WR RD D31 to D0 WEn D31 to D0 BS T2 Read Write Figure 10 6 Basic Timing of Basic Interface ...
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