749
Table B.1
Memory-Mapped Control Registers (cont)
Control Register
Module
*
1
Bus
*
2
Address
*
4
Size (Bits)
Access Size (Bits)
*
3
RWKAR
RTC
P
FFFFFED6
8
8
RDAYAR
RTC
P
FFFFFED8
8
8
RMONAR
RTC
P
FFFFFEDA
8
8
RCR1
RTC
P
FFFFFEDC
8
8
RCR2
RTC
P
FFFFFEDE
8
8
ICR0
INTC
I
FFFFFEE0
16
16
IPRA
INTC
I
FFFFFEE2
16
16
IPRB
INTC
I
FFFFFEE4
16
16
TOCR
TMU
P
FFFFFE90
8
8
TSTR
TMU
P
FFFFFE92
8
8
TCOR0
TMU
P
FFFFFE94
32
32
TCNT0
TMU
P
FFFFFE98
32
32
TCR0
TMU
P
FFFFFE9C
16
16
TCOR1
TMU
P
FFFFFEA0
32
32
TCNT1
TMU
P
FFFFFEA4
32
32
TCR1
TMU
P
FFFFFEA8
16
16
TCOR2
TMU
P
FFFFFEAC
32
32
TCNT2
TMU
P
FFFFFEB0
32
32
TCR2
TMU
P
FFFFFEB4
16
16
TCPR2
TMU
P
FFFFFEB8
32
32
SCSMR
SCI
P
FFFFFE80
8
8
SCBRR
SCI
P
FFFFFE82
8
8
SCSCR
SCI
P
FFFFFE84
8
8
SCTDR
SCI
P
FFFFFE86
8
8
SCSSR
SCI
P
FFFFFE88
8
8
SCRDR
SCI
P
FFFFFE8A
8
8
INTEVT2
INTC
I
4000000
32
32
IRR0
INTC
I
4000004
16
8
IRR1
INTC
I
4000006
16
8
IRR2
INTC
I
4000008
16
8
ICR1
INTC
I
4000010
16
16
ICR2
INTC
I
4000012
16
16
Содержание SH7709S
Страница 2: ...Hitachi SuperH RISC engine SH7709S Hardware Manual ADE 602 250 Rev 1 0 09 21 01 Hitachi Ltd ...
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Страница 292: ...273 T1 CKIO A25 to A0 CSn RD WR RD D31 to D0 WEn D31 to D0 BS T2 Read Write Figure 10 6 Basic Timing of Basic Interface ...
Страница 323: ...304 Tp TRr TRrw TRrw CKIO CKE CSn RAS3U RAS3L CASU CASL RD WR Figure 10 28 Synchronous DRAM Auto Refresh Timing ...
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