624
Channel Selection
Description
CH2
CH1
CH0
Single Mode
(MULTI = 0)
Multi Mode and Scan
Mode (MULTI = 1)
0
0
0
AN0 (Initial value)
AN0
1
AN1
AN0, AN1
1
0
AN2
AN0 to AN2
1
AN3
AN0 to AN3
1
0
0
AN4
AN4
1
AN5
AN4, AN5
1
0
AN6
AN4 to AN6
1
AN7
AN4 to AN7
20.2.3
A/D Control Register (ADCR)
Bit:
7
6
5
4
3
2
1
0
TRGE1
TRGE0
SCN
RESVD1 RESVD2
—
—
—
Initial value:
0
0
0
0
0
1
1
1
R/W:
R/W
R/W
R/W
R/W
R/W
R
R
R
ADCR is an 8-bit readable/writable register that enables or disables external triggering of A/D
conversion. ADCR is initialized to H'07 by a reset and in standby mode.
Bit 7 and 6—Trigger Enable (TRGE1, TRGE0): Enables or disables external triggering of A/D
conversion.
The TRGE1 and TRGE0 bits should only be set when conversion is not in progress.
Bit 7: TRGE1
Bit 6: TRGE0
Description
0
0
A/D conversion does not start when an external trigger is input
(Initial value)
0
1
1
0
1
1
A/D conversion starts at the falling edge of an input signal from
the external trigger pin (
ADTRG
)
Bit 5—Scan Mode (SCN): Selects multi mode or scan mode when the MULTI bit is set to 1. See
the description of bit 4 in section 20.2.2, A/D Control/Status Register (ADCSR).
Содержание SH7709S
Страница 2: ...Hitachi SuperH RISC engine SH7709S Hardware Manual ADE 602 250 Rev 1 0 09 21 01 Hitachi Ltd ...
Страница 75: ...56 ...
Страница 107: ...88 ...
Страница 125: ...106 ...
Страница 139: ...120 ...
Страница 203: ...184 ...
Страница 245: ...226 ...
Страница 292: ...273 T1 CKIO A25 to A0 CSn RD WR RD D31 to D0 WEn D31 to D0 BS T2 Read Write Figure 10 6 Basic Timing of Basic Interface ...
Страница 323: ...304 Tp TRr TRrw TRrw CKIO CKE CSn RAS3U RAS3L CASU CASL RD WR Figure 10 28 Synchronous DRAM Auto Refresh Timing ...
Страница 411: ...392 ...
Страница 609: ...590 ...
Страница 635: ...616 ...
Страница 663: ...644 ...
Страница 679: ...660 ...