651
Table 22.3
Pins of this LSI and Boundary Scan Register Bits (cont)
Bit
Pin Name
I/O
Bit
Pin Name
I/O
217
A7
OUT
187
CS4
/PTK2
OUT
216
A8
OUT
186
CS5
/
CE1A
/PTK3
OUT
215
A9
OUT
185
CS6
/
CE1B
OUT
214
A10
OUT
184
CE2A
/PTE4
OUT
213
A11
OUT
183
CE2B
/PTE5
OUT
212
A12
OUT
182
A0
Control
211
A13
OUT
181
A1
Control
210
A14
OUT
180
A2
Control
209
A15
OUT
179
A3
Control
208
A16
OUT
178
A4
Control
207
A17
OUT
177
A5
Control
206
A18
OUT
176
A6
Control
205
A19
OUT
175
A7
Control
204
A20
OUT
174
A8
Control
203
A21
OUT
173
A9
Control
202
A22
OUT
172
A10
Control
201
A23
OUT
171
A11
Control
200
A24
OUT
170
A12
Control
199
A25
OUT
169
A13
Control
198
BS
/PTK4
OUT
168
A14
Control
197
RD
OUT
167
A15
Control
196
WE0
/DQMLL
OUT
166
A16
Control
195
WE1
/DQMLU/
WE
OUT
165
A17
Control
194
WE2
/DQMUL/
ICIORD
/
PTK6
OUT
164
A18
Control
193
WE3
/DQMUU/
ICIOWR
/
PTK7
OUT
163
A19
Control
192
RD/
WR
OUT
162
A20
Control
191
AUDSYNC
/PTE7
OUT
161
A21
Control
190
CS0
/MCS0
OUT
160
A22
Control
189
CS2
/PTK0
OUT
159
A23
Control
188
CS3
/PTK1
OUT
158
A24
Control
Содержание SH7709S
Страница 2: ...Hitachi SuperH RISC engine SH7709S Hardware Manual ADE 602 250 Rev 1 0 09 21 01 Hitachi Ltd ...
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Страница 292: ...273 T1 CKIO A25 to A0 CSn RD WR RD D31 to D0 WEn D31 to D0 BS T2 Read Write Figure 10 6 Basic Timing of Basic Interface ...
Страница 323: ...304 Tp TRr TRrw TRrw CKIO CKE CSn RAS3U RAS3L CASU CASL RD WR Figure 10 28 Synchronous DRAM Auto Refresh Timing ...
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