742
Table A.8
Pin States (Synchronous DRAM/Big Endian)
32-Bit Bus Width
Pin
Byte
Access
(Address
4n)
Byte
Access
(Address
4n + 1)
Byte
Access
(Address
4n + 2)
Byte
Access
(Address
4n + 3)
Word
Access
(Address
4n)
Word
Access
(Address
4n + 2)
Longword
Access
CS6
to
CS2
,
CS0
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
RD
R
High
High
High
High
High
High
High
W
High
High
High
High
High
High
High
RD/
WR
R
High
High
High
High
High
High
High
W
Low
Low
Low
Low
Low
Low
Low
BS
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
RAS3U
/PTE[2]
High/Low
*
1
High/Low
*
1
High/Low
*
1
High/Low
*
1
High/Low
*
1
High/Low
*
1
High/Low
*
1
RAS3L
/PTJ[0]
Low/High
*
1
Low/High
*
1
Low/High
*
1
Low/High
*
1
Low/High
*
1
Low/High
*
1
Low/High
*
1
CASL
/PTJ[2]
Low
Low
Low
Low
Low
Low
Low
CASU
/PTJ[3]
High
High
High
High
High
High
High
WE0
/DQMLL
R
High
High
High
Low
High
Low
Low
W
High
High
High
Low
High
Low
Low
WE1
/DQMLU/
WE
R
High
High
Low
High
High
Low
Low
W
High
High
Low
High
High
Low
Low
WE2
/DQMUL/
ICIORD
/
R
High
Low
High
High
Low
High
Low
PTK[6]
W
High
Low
High
High
Low
High
Low
WE3
/DQMUU/
ICIOWR
/ R
Low
High
High
High
Low
High
Low
PTK[7]
W
Low
High
High
High
Low
High
Low
CE2A
/PTE[4]
High
High
High
High
High
High
High
CE2B
/PTE[5]
High
High
High
High
High
High
High
CKE/PTK[5]
High
*
2
High
*
2
High
*
2
High
*
2
High
*
2
High
*
2
High
*
2
WAIT
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
IOIS16
/PTG[7]
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
A25 to A0
Address
command
Address
command
Address
command
Address
command
Address
command
Address
command
Address
command
D7 to D0
Valid
data
Invalid
data
Invalid
data
Invalid
data
Valid
data
Invalid
data
Valid
data
D15 to D8
Invalid
data
Valid
data
Invalid
data
Invalid
data
Valid
data
Invalid
data
Valid
data
D23 to D16
Invalid
data
Invalid
data
Valid
data
Invalid
data
Invalid
data
Valid
data
Valid
data
D31 to D24
Invalid
data
Invalid
data
Invalid
data
Valid
data
Invalid
data
Valid
data
Valid
data
Notes:
*
1 Lower 32-MB access/ Upper 32-MB access/64-MB access
*
2 Normally high. Low in self-refreshing.
Содержание SH7709S
Страница 2: ...Hitachi SuperH RISC engine SH7709S Hardware Manual ADE 602 250 Rev 1 0 09 21 01 Hitachi Ltd ...
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Страница 292: ...273 T1 CKIO A25 to A0 CSn RD WR RD D31 to D0 WEn D31 to D0 BS T2 Read Write Figure 10 6 Basic Timing of Basic Interface ...
Страница 323: ...304 Tp TRr TRrw TRrw CKIO CKE CSn RAS3U RAS3L CASU CASL RD WR Figure 10 28 Synchronous DRAM Auto Refresh Timing ...
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