127
Table 6.3
IRL3
–
IRL0
/
IRLS3
–
IRLS0
Pins and Interrupt Levels
IRL3/
IRLS3
IRL2/
IRLS2
IRL1/
IRLS1
IRL0/
IRLS0
Interrupt Priority Level
Interrupt Request
0
0
0
0
15
Level 15 interrupt request
0
0
0
1
14
Level 14 interrupt request
0
0
1
0
13
Level 13 interrupt request
0
0
1
1
12
Level 12 interrupt request
0
1
0
0
11
Level 11 interrupt request
0
1
0
1
10
Level 10 interrupt request
0
1
1
0
9
Level 9 interrupt request
0
1
1
1
8
Level 8 interrupt request
1
0
0
0
7
Level 7 interrupt request
1
0
0
1
6
Level 6 interrupt request
1
0
1
0
5
Level 5 interrupt request
1
0
1
1
4
Level 4 interrupt request
1
1
0
0
3
Level 3 interrupt request
1
1
0
1
2
Level 2 interrupt request
1
1
1
0
1
Level 1 interrupt request
1
1
1
1
0
No interrupt request
A noise-cancellation feature is built in, and the IRL interrupt is not detected unless the levels
sampled at every peripheral module clock cycle remain unchanged for two consecutive cycles, so
that no transient level on the
IRL
/
IRLS
pin change is detected. In standby mode, as the peripheral
clock is stopped, noise cancellation is performed using the 32-kHz clock for the RTC instead.
Therefore when the RTC is not used, interruption by means of IRL interrupts cannot be performed
in standby mode.
The priority level of the IRL interrupt must not be lowered until the interrupt is accepted and
interrupt handling starts. However, the priority level can be changed to a higher one.
The interrupt mask bits (I3–I0) in the status register (SR) are not affected by
IRL
/
IRLS
interrupt
handling.
When the interrupt level of the IRL interrupt is higher than the level set by the I3-I0 bits in the SR,
the IRL interrupt can be used to recover from standby mode (however, this only applies when the
RTC is used for 32-kHz oscillator).
Содержание SH7709S
Страница 2: ...Hitachi SuperH RISC engine SH7709S Hardware Manual ADE 602 250 Rev 1 0 09 21 01 Hitachi Ltd ...
Страница 75: ...56 ...
Страница 107: ...88 ...
Страница 125: ...106 ...
Страница 139: ...120 ...
Страница 203: ...184 ...
Страница 245: ...226 ...
Страница 292: ...273 T1 CKIO A25 to A0 CSn RD WR RD D31 to D0 WEn D31 to D0 BS T2 Read Write Figure 10 6 Basic Timing of Basic Interface ...
Страница 323: ...304 Tp TRr TRrw TRrw CKIO CKE CSn RAS3U RAS3L CASU CASL RD WR Figure 10 28 Synchronous DRAM Auto Refresh Timing ...
Страница 411: ...392 ...
Страница 609: ...590 ...
Страница 635: ...616 ...
Страница 663: ...644 ...
Страница 679: ...660 ...