721
23.3.11
Delay Time Variation Due to Load Capacitance
A graph (reference data) of the variation in delay time when a load capacitance greater than that
stipulated (30 or 50 pF) is connected to this LSI's pins is shown below. The graph shown in figure
23.60 should be taken into consideration in the design process if the stipulated capacitance is
exceeded in connecting an external device.
If the connected load capacitance exceeds the range shown in figure 23.60, the graph will not be a
straight line.
+3
+2
+1
+0
+0
+10
+20
+30
+40
+50
Load Capacitance [pF]
Dela
y Time
[ns]
Figure 23.60 Load Capacitance vs. Delay Time
Содержание SH7709S
Страница 2: ...Hitachi SuperH RISC engine SH7709S Hardware Manual ADE 602 250 Rev 1 0 09 21 01 Hitachi Ltd ...
Страница 75: ...56 ...
Страница 107: ...88 ...
Страница 125: ...106 ...
Страница 139: ...120 ...
Страница 203: ...184 ...
Страница 245: ...226 ...
Страница 292: ...273 T1 CKIO A25 to A0 CSn RD WR RD D31 to D0 WEn D31 to D0 BS T2 Read Write Figure 10 6 Basic Timing of Basic Interface ...
Страница 323: ...304 Tp TRr TRrw TRrw CKIO CKE CSn RAS3U RAS3L CASU CASL RD WR Figure 10 28 Synchronous DRAM Auto Refresh Timing ...
Страница 411: ...392 ...
Страница 609: ...590 ...
Страница 635: ...616 ...
Страница 663: ...644 ...
Страница 679: ...660 ...