247
Bits 9 to 7—Area 4 Wait Control (A4W2, A4W1, A4W0): Specify the number of wait states
inserted in physical space area 4.
Description
Bit 9: A4W2
Bit 8: A4W1
Bit 7: A4W0
Inserted Wait State
WAIT
Pin
0
0
0
0
Ignored
1
1
Enabled
1
0
2
Enabled
1
3
Enabled
1
0
0
4
Enabled
1
6
Enabled
1
0
8
Enabled
1
10
Enabled (Initial value)
Bits 6 and 5—Area 3 Wait Control (A3W1, A3W0): Specify the number of wait states inserted
in physical space area 3.
•
For Ordinary Memory
Description
Bit 6: A3W1
Bit 5: A3W0
Inserted Wait States
WAIT
Pin
0
0
0
Ignored
1
1
Enabled
1
0
2
Enabled
1
3
Enabled
(Initial value)
•
For Synchronous DRAM
Description
Bit 6: A3W1
Bit 5: A3W0
Synchronous DRAM: CAS Latency
0
0
1
1
1
1
0
2
1
3
(Initial value)
Содержание SH7709S
Страница 2: ...Hitachi SuperH RISC engine SH7709S Hardware Manual ADE 602 250 Rev 1 0 09 21 01 Hitachi Ltd ...
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Страница 292: ...273 T1 CKIO A25 to A0 CSn RD WR RD D31 to D0 WEn D31 to D0 BS T2 Read Write Figure 10 6 Basic Timing of Basic Interface ...
Страница 323: ...304 Tp TRr TRrw TRrw CKIO CKE CSn RAS3U RAS3L CASU CASL RD WR Figure 10 28 Synchronous DRAM Auto Refresh Timing ...
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