200
Standby to Manual Reset
CKIO, CKIO2
*
6
STATUS
Normal
*
4
Normal
*
4
Oscillation stops
Standby
*
3
Reset
*
2
0 to 20 Bcyc
*
5
Reset
RESETM
*
1
Notes:
*
1 When standby mode is cleared with a manual reset, the WDT does not count.
Keep
RESETM
low during the PLL’s oscillation settling time.
*
2 Reset:
HH (STATUS1 high, STATUS0 high)
*
3 Standby: LH (STATUS1 low, STATUS0 high)
*
4 Normal:
LL (STATUS1 low, STATUS0 low)
*
5 Bcyc:
Bus clock cycle
*
6 The CKIO2 output is available only in clock modes 0, 1, and 2.
Figure 8.6 Standby to Manual Reset STATUS Output
8.6.3
Timing for Canceling Sleep Mode
Sleep to Interrupt
CKIO, CKIO2
*
3
STATUS
Normal
*
2
Normal
*
2
Sleep
*
1
Interrupt request
Notes:
*
1 Sleep:
HL (STATUS1 high, STATUS0 low)
*
2 Normal: LL (STATUS1 low, STATUS0 low)
*
3 The CKIO2 output is available only in clock modes 0, 1, and 2.
Figure 8.7 Sleep to Interrupt STATUS Output
Содержание SH7709S
Страница 2: ...Hitachi SuperH RISC engine SH7709S Hardware Manual ADE 602 250 Rev 1 0 09 21 01 Hitachi Ltd ...
Страница 75: ...56 ...
Страница 107: ...88 ...
Страница 125: ...106 ...
Страница 139: ...120 ...
Страница 203: ...184 ...
Страница 245: ...226 ...
Страница 292: ...273 T1 CKIO A25 to A0 CSn RD WR RD D31 to D0 WEn D31 to D0 BS T2 Read Write Figure 10 6 Basic Timing of Basic Interface ...
Страница 323: ...304 Tp TRr TRrw TRrw CKIO CKE CSn RAS3U RAS3L CASU CASL RD WR Figure 10 28 Synchronous DRAM Auto Refresh Timing ...
Страница 411: ...392 ...
Страница 609: ...590 ...
Страница 635: ...616 ...
Страница 663: ...644 ...
Страница 679: ...660 ...