Hitachi SH7709S, Руководство по оборудованию

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679
23.3.2 Control Signal Timing
Table 23.6 Control Signal Timing
(Vcc = 3.3 ± 0.3 V, Vcc = 1.55 to 2.15 V, AVcc = 3.3 ± 0.3 V, Ta = –20 to 75°C)
to 66 *
2
Item Symbol Min Max Unit Figure
RESETP
pulse width t
RESPW
20 *
3
— tcyc 23.11,
RESETP
setup time
* 1
t
RESPS
20 — ns 23.12
RESETP
hold time t
RESPH
4 — ns
RESETM
pulse width t
RESMW
20 *
4
— tcyc
RESETM
setup time t
RESMS
6 — ns
RESETM
hold time t
RESMH
34 — ns
BREQ
setup time t
BREQS
6 — ns 23.14
BREQ
hold time t
BREQH
4 — ns
NMI setup time *
1
t
NMIS
10 — ns 23.12
NMI hold time t
NMIH
4 — ns
IRQ5–IRQ0 setup time *
1
t
IRQS
10 — ns
IRQ5–IRQ0 hold time t
IRQH
4 — ns
IRQOUT
delay time t
IRQOD
— 10 ns 23.13
BACK
delay time t
BACKD
— 10 ns 23.14,
STATUS1, STATUS0 delay time t
STD
— 10 ns 23.15
Bus tri-state delay time 1 t
BOFF1
0 15 ns
Bus tri-state delay time 2 t
BOFF2
0 15 ns
Bus buffer-on time 1 t
BON1
0 15 ns
Bus buffer-on time 2 t
BON2
0 15 ns
Notes:
*
1
RESETP
, NMI, and IRQ5 to IRQ0 are asynchronous. Changes are detected at the clock
fall when the setup shown is used. When the setup cannot be used, detection can be
delayed until the next clock falls.
* 2 The upper limit of the external bus clock is 66 MHz.
*
3 In the standby mode, t
RESPW
= t
OSC1
(100 µs) when XTAL oscillation is continued and t
RESPW
= t
OSC2
(10 ms) when XTAL oscillation is off. In the sleep mode, t
RESPW
= t
PLL1
(100 µs).
When the clock multiplication ratio is changed, t
RESPW
= t
PLL1
(100 µs).
* 4 In the standby mode, t
RESMW
= t
OSC2
(10 ms). In the sleep mode,
RESETM
must be
kept low until STATUS (0-1) changes to reset (HH). When the clock multiplication ratio
is changed,
RESETM
must be kept low until STATUS (0-1) changes to reset (HH).