6
1.2
Block Diagram
MMU
TLB
SH-3
CPU
UBC
SCI
TMU
RTC
IrDA
SCIF
ADC
DAC
AUD
BRIDGE
DMAC
CMT
I/O port
External bus
interface
BSC
CCN
CACHE
ASERAM
UDI
INTC
CPG/WDT
Peripheral bus 1
Peripheral bus 2
L bus
I bus 1
I bus 2
Legend:
ADC:
ASERAM:
AUD:
BSC:
CACHE:
CCN:
CMT:
CPG/WDT:
CPU:
DAC:
DMAC:
H-UDI:
A/D converter
ASE memory
Advanced user debugger
Bus state controller
Cache memory
Cache memory controller
Compare match timer
Clock pulse generator/watchdog timer
Central processing unit
D/A converter
Direct memory access controller
Hitachi user-debugging interface
INTC:
IrDA:
MMU:
RTC:
SCI:
SCIF:
TLB:
TMU:
UBC:
Interrupt controller
Serial communicatiion interface (with IrDA)
Memory management unit
Realtime clock
Serial communication interface (with smart card interface)
Serial communication interface (with FIFO)
Address translation buffer
Timer unit
User break controller
Figure 1.1 Block Diagram
Содержание SH7709S
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Страница 292: ...273 T1 CKIO A25 to A0 CSn RD WR RD D31 to D0 WEn D31 to D0 BS T2 Read Write Figure 10 6 Basic Timing of Basic Interface ...
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