255
Bits 9, 3, and 2—Area 5
OE
/
WE
Negate Address Delay (A5TEH2, A5TEH1, A5TEH0):
Specify the address hold delay time from
OE
/
WE
negation for the PCMCIA interface connected
to area 5.
Bit 9:
A5TEH2
Bit 3:
A5TEH1
Bit 2:
A5TEH0
Description
0
0
0
0.5-cycle delay
(Initial value)
1
1.5-cycle delay
1
0
2.5-cycle delay
1
3.5-cycle delay
1
0
0
4.5-cycle delay
1
5.5-cycle delay
1
0
6.5-cycle delay
1
7.5-cycle delay
Bits 8, 1, and 0—Area 6
OE
/
WE
Negate Address Delay (A6TEH2, A6TEH1, A6TEH0):
Specify the address hold delay time from
OE
/
WE
negation for the PCMCIA interface connected
to area 6.
Bit 8:
A6TEH2
Bit 1:
A6TEH1
Bit 0:
A6TEH0
Description
0
0
0
0.5-cycle delay
(Initial value)
1
1.5-cycle delay
1
0
2.5-cycle delay
1
3.5-cycle delay
1
0
0
4.5-cycle delay
1
5.5-cycle delay
1
0
6.5-cycle delay
1
7.5-cycle delay
Содержание SH7709S
Страница 2: ...Hitachi SuperH RISC engine SH7709S Hardware Manual ADE 602 250 Rev 1 0 09 21 01 Hitachi Ltd ...
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Страница 292: ...273 T1 CKIO A25 to A0 CSn RD WR RD D31 to D0 WEn D31 to D0 BS T2 Read Write Figure 10 6 Basic Timing of Basic Interface ...
Страница 323: ...304 Tp TRr TRrw TRrw CKIO CKE CSn RAS3U RAS3L CASU CASL RD WR Figure 10 28 Synchronous DRAM Auto Refresh Timing ...
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