692
CKIO
A12 or A10
RD/
WR
CSn
RAS
CAS
BS
DQMxx
CKE
(High)
A25 to A16
A15 to A0
Tr
Tc1
Tc2/Td1 Tc3/Td2
Tc4/Td3
Td4
(Tpc)
(Tpc)
,,
,,
D31 to D0
Row address
Row
address
Read A
command
Read command
Row
address
Column address (1-4)
tAD
tAD
tAD
tAD
tAD
tAD
tAD
tAD
tAD
tCSD3
tCSD3
tRWD
tRWD
tRASD2
tDQMD
tBSD
tBSD
tRDS2 tRDH2
tRDS2 tRDH2
tDQMD
tRASD2
tCASD2
tCASD2
tDAKD1
tDAKD1
DACKn
Figure 23.24 Synchronous DRAM Read Bus Cycle (Burst Read (Single Read
×
4), RCD
=
0,
CAS Latency
=
1, TPC
=
1)
Содержание SH7709S
Страница 2: ...Hitachi SuperH RISC engine SH7709S Hardware Manual ADE 602 250 Rev 1 0 09 21 01 Hitachi Ltd ...
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Страница 292: ...273 T1 CKIO A25 to A0 CSn RD WR RD D31 to D0 WEn D31 to D0 BS T2 Read Write Figure 10 6 Basic Timing of Basic Interface ...
Страница 323: ...304 Tp TRr TRrw TRrw CKIO CKE CSn RAS3U RAS3L CASU CASL RD WR Figure 10 28 Synchronous DRAM Auto Refresh Timing ...
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