196
8.6
Timing of STATUS Pin Changes
The timing of STATUS1 and STATUS0 pin changes is shown in figures 8.1 through 8.8.
8.6.1
Timing for Resets
Power-On Reset
CKIO, CKIO2
*
4
RESETP
STATUS
Normal
*
2
Normal
*
2
Reset
*
1
PLL settling
time
0 to 5 Bcyc
*
3
0 to 30 Bcyc
*
3
RESETOUT
Notes:
*
1 Reset:
HH (STATUS1 high, STATUS0 high)
*
2 Normal:
LL (STATUS1 low, STATUS0 low)
*
3 Bcyc:
Bus clock cycle
*
4 The CKIO2 output is available only in clock modes 0, 1, and 2.
Figure 8.2 Power-On Reset (Clock Modes 0, 1, 2, and 7) STATUS Output
Содержание SH7709S
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Страница 292: ...273 T1 CKIO A25 to A0 CSn RD WR RD D31 to D0 WEn D31 to D0 BS T2 Read Write Figure 10 6 Basic Timing of Basic Interface ...
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