602
19.7.2
Port F Data Register (PFDR)
Bit:
7
6
5
4
3
2
1
0
PF7DT
PF6DT
PF5DT
PF4DT
PF3DT
PF2DT
PF1DT
PF0DT
Initial value:
*
*
*
*
*
*
*
*
R/W:
R
R
R
R
R
R
R
R
Note:
*
Undefined
The port F data register (PFDR) is an 8-bit read-only register that stores data for pins PTF7 to
PTF0. Bits PF7DT to PF0DT correspond to pins PTF7 to PTF0. When the function is general
input port, if the port is read the corresponding pin level is read. Table 19.12 shows the function of
PFDR.
PFDR is initialized by a power-on reset, after which the general input port function (pull-up MOS
on) is set as the initial pin function, and the corresponding pin levels are read.
Table 19.12 Port F Data Register (PFDR) Read/Write Operations
PFnMD1
PFnMD0
Pin State
Read
Write
0
0
Other function
(See table 18.1)
H'00
Ignored (no effect on pin state)
1
Reserved
H'00
Ignored (no effect on pin state)
1
0
Input (Pull-up
MOS on)
Pin state
Ignored (no effect on pin state)
1
Input (Pull-up
MOS off)
Pin state
Ignored (no effect on pin state)
(n = 0 to 7)
Содержание SH7709S
Страница 2: ...Hitachi SuperH RISC engine SH7709S Hardware Manual ADE 602 250 Rev 1 0 09 21 01 Hitachi Ltd ...
Страница 75: ...56 ...
Страница 107: ...88 ...
Страница 125: ...106 ...
Страница 139: ...120 ...
Страница 203: ...184 ...
Страница 245: ...226 ...
Страница 292: ...273 T1 CKIO A25 to A0 CSn RD WR RD D31 to D0 WEn D31 to D0 BS T2 Read Write Figure 10 6 Basic Timing of Basic Interface ...
Страница 323: ...304 Tp TRr TRrw TRrw CKIO CKE CSn RAS3U RAS3L CASU CASL RD WR Figure 10 28 Synchronous DRAM Auto Refresh Timing ...
Страница 411: ...392 ...
Страница 609: ...590 ...
Страница 635: ...616 ...
Страница 663: ...644 ...
Страница 679: ...660 ...