751
Table B.1
Memory-Mapped Control Registers (cont)
Control Register
Module
*
1
Bus
*
2
Address
*
4
Size (Bits)
Access Size (Bits)
*
3
ADDRDL
A/D
P
400008E
8
8,16
*
5
ADCSR
A/D
P
4000090
8
8,16,32
*
5,
*
6
ADCR
A/D
P
4000092
8
8,16
DADR0
D/A
P
40000A0
8
8,16,32
*
5,
*
6
DADR1
D/A
P
40000A2
8
8,16
*
5
DACR
D/A
P
40000A4
8
8,16,32
PACR
PORT
P
4000100
16
16
PBCR
PORT
P
4000102
16
16
PCCR
PORT
P
4000104
16
16
PDCR
PORT
P
4000106
16
16
PECR
PORT
P
4000108
16
16
PFCR
PORT
P
400010A
16
16
PGCR
PORT
P
400010C
16
16
PHCR
PORT
P
400010E
16
16
PJCR
PORT
P
4000110
16
16
PKCR
PORT
P
4000112
16
16
PLCR
PORT
P
4000114
16
16
SCPCR
PORT
P
4000116
16
16
PADR
PORT
P
4000120
8
8
PBDR
PORT
P
4000122
8
8
PCDR
PORT
P
4000124
8
8
PDDR
PORT
P
4000126
8
8
PEDR
PORT
P
4000128
8
8
PFDR
PORT
P
400012A
8
8
PGDR
PORT
P
400012C
8
8
PHDR
PORT
P
400012E
8
8
PJDR
PORT
P
4000130
8
8
PKDR
PORT
P
4000132
8
8
PLDR
PORT
P
4000134
8
8
SCPDR
PORT
P
4000136
8
8
SCSMR1
IrDA
P
4000140
8
8
SCBRR1
IrDA
P
4000142
8
8
Содержание SH7709S
Страница 2: ...Hitachi SuperH RISC engine SH7709S Hardware Manual ADE 602 250 Rev 1 0 09 21 01 Hitachi Ltd ...
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Страница 292: ...273 T1 CKIO A25 to A0 CSn RD WR RD D31 to D0 WEn D31 to D0 BS T2 Read Write Figure 10 6 Basic Timing of Basic Interface ...
Страница 323: ...304 Tp TRr TRrw TRrw CKIO CKE CSn RAS3U RAS3L CASU CASL RD WR Figure 10 28 Synchronous DRAM Auto Refresh Timing ...
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