726
Table A.1
Pin States during Resets, Power-Down States, and Bus-Released State (cont)
Reset
Power-Down
Category
Pin
Power-On
Reset
Manual
Reset
Standby
Sleep
Bus
Released
Port
ASEMD0
/PTG[6]
I
I
Z
I
I
PTJ[1]
H
OP
*
3
ZOK
*
4
OP
*
3
ZOP
*
4
PTE[1]
*
13
V
OP
*
3
ZOK
*
4
OP
*
3
ZOP
*
4
PTE[6]
V
OP
*
3
ZOK
*
4
OP
*
3
ZOP
*
4
PTE[3]
V
OP
*
3
ZOK
*
4
OP
*
3
ZOP
*
4
PTJ[4]
H
OP
*
3
ZOK
*
4
OP
*
3
ZOP
*
4
PTJ[5]
H
OP
*
3
ZOK
*
4
OP
*
3
ZOP
*
4
Analog
AN[5:0]/PTL[5:0]
Z
ZI
*
7
Z
I
I
AN[6:7]/DA[1:0]/
PTL[6:7]
Z
ZI
*
7
OZ
*
12
IO
*
9
IO
*
9
I:
Input
O: Output
H: High-level output
L: Low-level output
Z: High impedance
P: Input or output depending on register setting
K: Input pin is high impedance, output pin holds its state
V: I/O buffer off, pull-up MOS on
Notes:
*
1 Depending on the clock mode (MD2–MD0 setting).
*
2 Z when the port function is used.
*
3 K or P when the port function is used.
*
4 K or P when the port function is used. Z or O when the port function is not used
depending on register setting.
*
5 K or P when the port function is used. I or O when the port function is not used
depending on register setting.
*
6 Depending on register setting.
*
7 I or O when the port function is used.
*
8 Input Schmitt buffers and pull-up MOS of IRQ[5:0] and ADTRG are on; other inputs are
off.
*
9 O when DA output is enabled; otherwise I depending on register setting.
*
10 In standby mode, Z or L depending on register setting.
*
11 In standby mode, Z or H depending on register setting.
*
12 O when DA output is enabled; Z otherwise.
*
13 In a power-on reset, leave open or input a high level.
Содержание SH7709S
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Страница 292: ...273 T1 CKIO A25 to A0 CSn RD WR RD D31 to D0 WEn D31 to D0 BS T2 Read Write Figure 10 6 Basic Timing of Basic Interface ...
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