42
Table 2.7
Arithmetic Instructions (cont)
Instruction
Operation
Code
Privileged
Mode
Cycles T Bit
DMULS.L Rm,Rn
Signed operation of
Rn
×
Rm
→
MACH,
MACL 32
×
32
→
64 bits
0011nnnnmmmm1101
—
2(to 5)
*
—
DMULU.L Rm,Rn
Unsigned operation of
Rn
×
Rm
→
MACH,
MACL 32
×
32
→
64 bits
0011nnnnmmmm0101
—
2(to 5)
*
—
DT
Rn
Rn – 1
→
Rn, if Rn
=
0, 1
→
T, else 0
→
T
0100nnnn00010000
—
1
Comparison
result
EXTS.B Rm,Rn
A byte in Rm is sign-
extended
→
Rn
0110nnnnmmmm1110
—
1
—
EXTS.W Rm,Rn
A word in Rm is sign-
extended
→
Rn
0110nnnnmmmm1111
—
1
—
EXTU.B Rm,Rn
A byte in Rm is zero-
extended
→
Rn
0110nnnnmmmm1100
—
1
—
EXTU.W Rm,Rn
A word in Rm is zero-
extended
→
Rn
0110nnnnmmmm1101
—
1
—
MAC.L
@Rm+,@Rn+
Signed operation of (Rn)
×
(Rm)
+
MAC
→
MAC,
Rn + 4
→
Rn,
Rm + 4
→
Rm
32
×
32 + 64
→
64 bits
0000nnnnmmmm1111
—
2(to 5)
*
—
MAC.W
@Rm+,@Rn+
Signed operation of (Rn)
×
(Rm)
+
MAC
→
MAC,
Rn + 2
→
Rn,
Rm + 2
→
Rm
16
×
16 + 64
→
64 bits
0100nnnnmmmm1111
—
2(to 5)
*
—
MUL.L
Rm,Rn
Rn
×
Rm
→
MACL
32
×
32
→
32 bits
0000nnnnmmmm0111
—
2(to 5)
*
—
MULS.W Rm,Rn
Signed operation of Rn
×
Rm
→
MAC
16
×
16
→
32 bits
0010nnnnmmmm1111
—
1(to 3)
*
—
MULU.W Rm,Rn
Unsigned operation of
Rn
×
Rm
→
MAC
16
×
16
→
32 bits
0010nnnnmmmm1110
—
1(to 3)
*
—
Содержание SH7709S
Страница 2: ...Hitachi SuperH RISC engine SH7709S Hardware Manual ADE 602 250 Rev 1 0 09 21 01 Hitachi Ltd ...
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Страница 292: ...273 T1 CKIO A25 to A0 CSn RD WR RD D31 to D0 WEn D31 to D0 BS T2 Read Write Figure 10 6 Basic Timing of Basic Interface ...
Страница 323: ...304 Tp TRr TRrw TRrw CKIO CKE CSn RAS3U RAS3L CASU CASL RD WR Figure 10 28 Synchronous DRAM Auto Refresh Timing ...
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