182
Break Condition Specified to a DMAC Data Access Cycle
1. Register specifications:
BARA = H'00314156, BAMRA = H'00000000, BBRA = H'0094, BARB = H'00055555,
BAMRB = H'00000000, BBRB = H'00A9, BDRB = H'00000078, BDMRB = H'0000000F,
BRCR = H'00000080, BASRA = H'80, BASRB = H'70
Specified conditions: Channel A/channel B independent mode
•
Channel A
Address:
H'00314156, Address mask: H'00000000, ASID: H'80
Bus cycle: DMAC/instruction fetch/read (operand size is not included in the condition)
•
Channel B
Address:
H'00055555, Address mask: H'00000000, ASID: H'70
Data:
H'00000078, Data mask: H'0000000F
Bus cycle: DMAC/data access/write/byte
On channel A, no user break occurs since instruction fetch is not performed in DMAC cycles.
On channel B, a user break occurs with ASID = H'70 when the DMAC writes byte H'7* in
address H'00055555.
7.3.8
Notes
1. Only CPU can read/write UBC registers.
2. UBC cannot monitor CPU and DMAC access in the same channel.
3. Notes in specification of sequential break are described below:
a. A condition match occurs when B-channel match occurs in a bus cycle after an A-channel
match occurs in another bus cycle in sequential break setting. Therefore, no condition
match occurs even if a bus cycle, in which an A-channel match and a channel B match
occur simultaneously, is set.
b. Since the CPU has a pipeline configuration, the pipeline determines the order of an
instruction fetch cycle and a memory cycle. Therefore, when a channel condition matches
in the order of bus cycles, a sequential condition is satisfied.
c. When the bus cycle condition for channel A is specified as a break before execution
(PCBA = 0 in BRCR) and an instruction fetch cycle (in BBRA), the attention is as follows.
A break is issued and condition match flags in BRCR are set to 1, when the bus cycle
conditions both for channels A and B match simultaneously.
4. The change of a UBC register value is executed in MA (memory access) stage. Therefore, even
if the break condition matches in the instruction fetch address following the instruction in
which the pre-execution break is specified as the break condition, no break occurs. In order to
know the timing UBC register is changed, read the last written register. Instructions after then
are valid for the newly written register value.
Содержание SH7709S
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