523
Bit 5—Parity Enable (PE): Selects whether to add a parity bit to transmit data and to check the
parity of receive data.
Bit 5: PE
Description
0
Parity bit not added or checked
(Initial value)
1
Parity bit added and checked
*
Note:
*
When PE is set to 1, an even or odd parity bit is added to transmit data, depending on the
parity mode (O/
E
) setting. Receive data parity is checked according to the even/odd (O/
E
)
mode setting.
Bit 4—Parity Mode (O/
E
): Selects even or odd parity when parity bits are added and checked.
The O/
E
setting is used only when the parity enable bit (PE) is set to 1 to enable parity addition
and checking. The O/
E
setting is ignored when parity addition and checking is disabled.
Bit 4: O/
E
Description
0
Even parity
*
1
(Initial value)
1
Odd parity
*
2
Notes:
*
1 If even parity is selected, the parity bit is added to transmit data to make an even
number of 1s in the transmitted character and parity bit combined. Receive data is
checked to see if it has an even number of 1s in the received character and parity bit
combined.
*
2 If odd parity is selected, the parity bit is added to transmit data to make an odd number
of 1s in the transmitted character and parity bit combined. Receive data is checked to
see if it has an odd number of 1s in the received character and parity bit combined.
Bit 3—Stop Bit Length (STOP): Selects one or two bits as the stop bit length.
When receiving, only the first stop bit is checked, regardless of the STOP bit setting. If the second
stop bit is 1, it is treated as a stop bit, but if the second stop bit is 0, it is treated as the start bit of
the next incoming character.
Bit 3: STOP
Description
0
One stop bit
*
1
(Initial value)
1
Two stop bits
*
2
Notes:
*
1 When transmitting, a single 1-bit is added at the end of each transmitted character.
*
2 When transmitting, two 1-bits are added at the end of each transmitted character.
Bit 2—Reserved: This bit is always read as 0. The write value should always be 0.
Содержание SH7709S
Страница 2: ...Hitachi SuperH RISC engine SH7709S Hardware Manual ADE 602 250 Rev 1 0 09 21 01 Hitachi Ltd ...
Страница 75: ...56 ...
Страница 107: ...88 ...
Страница 125: ...106 ...
Страница 139: ...120 ...
Страница 203: ...184 ...
Страница 245: ...226 ...
Страница 292: ...273 T1 CKIO A25 to A0 CSn RD WR RD D31 to D0 WEn D31 to D0 BS T2 Read Write Figure 10 6 Basic Timing of Basic Interface ...
Страница 323: ...304 Tp TRr TRrw TRrw CKIO CKE CSn RAS3U RAS3L CASU CASL RD WR Figure 10 28 Synchronous DRAM Auto Refresh Timing ...
Страница 411: ...392 ...
Страница 609: ...590 ...
Страница 635: ...616 ...
Страница 663: ...644 ...
Страница 679: ...660 ...