287
Transfer source address
Transfer destination address
+4
+8
+12
A25-A0
CKIO
CSn
RAS
CAS
WEn
RD/
WR
DACKn
D31-D0
Data read cycle
(1st cycle)
(2nd cycle)
Data write cycle
Note: In transfer between external memories, with DACK output in the read cycle, DACK
output timing is the same as that of
CSn
.
Figure 10.15 Example of DMA Transfer Timing in the Direct Address Mode in Dual Mode
(16-byte Transfer, Transfer Source: Synchronous DRAM, Transfer Destination: Normal
Memory)
Содержание SH7709S
Страница 2: ...Hitachi SuperH RISC engine SH7709S Hardware Manual ADE 602 250 Rev 1 0 09 21 01 Hitachi Ltd ...
Страница 75: ...56 ...
Страница 107: ...88 ...
Страница 125: ...106 ...
Страница 139: ...120 ...
Страница 203: ...184 ...
Страница 245: ...226 ...
Страница 292: ...273 T1 CKIO A25 to A0 CSn RD WR RD D31 to D0 WEn D31 to D0 BS T2 Read Write Figure 10 6 Basic Timing of Basic Interface ...
Страница 323: ...304 Tp TRr TRrw TRrw CKIO CKE CSn RAS3U RAS3L CASU CASL RD WR Figure 10 28 Synchronous DRAM Auto Refresh Timing ...
Страница 411: ...392 ...
Страница 609: ...590 ...
Страница 635: ...616 ...
Страница 663: ...644 ...
Страница 679: ...660 ...