286
output cycles Tc1-Tc4 to the first read data latch cycle, Td1, can be specified as 1 to 3 cycles
independently for areas 2 and 3 by means of bits A2W1 and A2W0 or A3W1 and A3W0 in
WCR2. This number of cycles corresponds to the number of synchronous DRAM CAS latency
cycles.
Transfer
source address
+4
+8
+12
Transfer
destination address
+4
+8
+12
Data read cycle
Data write cycle
(1st cycle)
(2nd cycle)
A25-A0
CKIO
CSn
RD
WEm
DACKn
D31-D0
Note: In transfer between external memories, with DACK output in the read cycle, DACK
output timing is the same as that of
CSn
.
Figure 10.14 Example of DMA Transfer Timing in the Direct Address Mode in Dual Mode
(16-byte Transfer, Transfer Source: Normal Memory, Transfer Destination: Normal
Memory)
Содержание SH7709S
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Страница 292: ...273 T1 CKIO A25 to A0 CSn RD WR RD D31 to D0 WEn D31 to D0 BS T2 Read Write Figure 10 6 Basic Timing of Basic Interface ...
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