47
Table 2.11 lists the SH7709S system control instructions.
Table 2.11
System Control Instructions
Instruction
Operation
Code
Privileged
Mode
Cycles T Bit
CLRMAC
0
→
MACH, MACL
0000000000101000
—
1
—
CLRS
0
→
S
0000000001001000
—
1
—
CLRT
0
→
T
0000000000001000
—
1
0
LDC
Rm,SR
Rm
→
SR
0100mmmm00001110
5
LSB
LDC
Rm,GBR
Rm
→
GBR
0100mmmm00011110
—
3
—
LDC
Rm,VBR
Rm
→
VBR
0100mmmm00101110
3
—
LDC
Rm,SSR
Rm
→
SSR
0100mmmm00111110
3
—
LDC
Rm,SPC
Rm
→
SPC
0100mmmm01001110
3
—
LDC
Rm,R0_BANK
Rm
→
R0_BANK
0100mmmm10001110
3
—
LDC
Rm,R1_BANK
Rm
→
R1_BANK
0100mmmm10011110
3
—
LDC
Rm,R2_BANK
Rm
→
R2_BANK
0100mmmm10101110
3
—
LDC
Rm,R3_BANK
Rm
→
R3_BANK
0100mmmm10111110
3
—
LDC
Rm,R4_BANK
Rm
→
R4_BANK
0100mmmm11001110
3
—
LDC
Rm,R5_BANK
Rm
→
R5_BANK
0100mmmm11011110
3
—
LDC
Rm,R6_BANK
Rm
→
R6_BANK
0100mmmm11101110
3
—
LDC
Rm,R7_BANK
Rm
→
R7_BANK
0100mmmm11111110
3
—
LDC.L @Rm+,SR
(Rm)
→
SR, Rm + 4
→
Rm
0100mmmm00000111
7
LSB
LDC.L @Rm+,GBR
(Rm)
→
GBR, Rm + 4
→
Rm
0100mmmm00010111
—
5
—
LDC.L @Rm+,VBR
(Rm)
→
VBR, Rm + 4
→
Rm
0100mmmm00100111
5
—
LDC.L @Rm+,SSR
(Rm)
→
SSR, Rm + 4
→
Rm
0100mmmm00110111
5
—
LDC.L @Rm+,SPC
(Rm)
→
SPC, Rm + 4
→
Rm
0100mmmm01000111
5
—
LDC.L @Rm+,
R0_BANK
(Rm)
→
R0_BANK,
Rm + 4
→
Rm
0100mmmm10000111
5
—
LDC.L @Rm+,
R1_BANK
(Rm)
→
R1_BANK,
Rm + 4
→
Rm
0100mmmm10010111
5
—
LDC.L @Rm+,
R2_BANK
(Rm)
→
R2_BANK,
Rm + 4
→
Rm
0100mmmm10100111
5
—
LDC.L @Rm+,
R3_BANK
(Rm)
→
R3_BANK,
Rm + 4
→
Rm
0100mmmm10110111
5
—
Содержание SH7709S
Страница 2: ...Hitachi SuperH RISC engine SH7709S Hardware Manual ADE 602 250 Rev 1 0 09 21 01 Hitachi Ltd ...
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Страница 292: ...273 T1 CKIO A25 to A0 CSn RD WR RD D31 to D0 WEn D31 to D0 BS T2 Read Write Figure 10 6 Basic Timing of Basic Interface ...
Страница 323: ...304 Tp TRr TRrw TRrw CKIO CKE CSn RAS3U RAS3L CASU CASL RD WR Figure 10 28 Synchronous DRAM Auto Refresh Timing ...
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