189
8.2.2
Standby Control Register 2 (STBCR2)
The standby control register 2 (STBCR2) is a readable/writable 8-bit register that sets the power-
down mode. STBCR2 is initialized to H'00 by a power-on reset.
Bit:
7
6
5
4
3
2
1
0
MDCHG MSTP8
MSTP7
MSTP6
MSTP5
MSTP4
MSTP3
Initial value:
0
0
0
0
0
0
0
0
R/W:
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit 7—Reserved: The write value set in the program should always be 1.
Bit 6—Pin MD5 to MD0 Control (MDCHG): Specifies whether or not pins MD5 to MD0 are
changed in standby mode. When this bit is set to 1, the MD5 to MD0 pin values are latched when
returning from standby mode by means of a reset or interrupt.
Bit 6: MDCHG
Description
0
Pins MD5 to MD0 are not changed in standby mode
(Initial value)
1
Pins MD5 to MD0 are changed in standby mode
Bit 5— Module Stop 8 (MSTP8): Specifies halting of the clock supply to the user break
controller UBC (an on-chip peripheral module). When the MSTP8 bit is set to 1, the supply of the
clock to the UBC is halted.
Bit 5: MSTP8
Description
0
UBC runs
(Initial value)
1
Clock supply to UBC is halted
Bit 4—Module Stop 7 (MSTP7): Specifies halting of the clock supply to the DMAC (an on-chip
peripheral module). When the MSTP7 bit is set to 1, the supply of the clock to the DMAC is
halted.
Bit 4: MSTP7
Description
0
DMAC runs
(Initial value)
1
Clock supply to DMAC halted
Bit 3—Module Stop 6 (MSTP6): Specifies halting of the clock supply to the DAC (an on-chip
peripheral module). When the MSTP6 bit is set to 1, the supply of the clock to the DAC is halted.
Содержание SH7709S
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Страница 292: ...273 T1 CKIO A25 to A0 CSn RD WR RD D31 to D0 WEn D31 to D0 BS T2 Read Write Figure 10 6 Basic Timing of Basic Interface ...
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