1096
ADCR—A/D Control Register
H'FF99
A/D
7
TRGS1
0
R/W
6
TRGS0
0
R/W
5
—
1
—
4
—
1
—
3
CKS1
0
R/W
0
—
1
—
2
CKS0
0
R/W
1
—
1
—
Time trigger select 1, 0
Clock select 1, 0
TRGS1 TRGS0
Description
0
0
Enables starting of A/D conversion by software.
1
Enables starting of A/D conversion by TPU conversion start trigger.
1
0
Enables starting of A/D conversion by 8-bit timer conversion start trigger.
1
Enables starting of A/D conversion by external trigger pin (ADTRG).
CKS1 CKS0
Description
0
0
Conversion time= 530 states (Max.)
1
Conversion time= 266 states (Max.)
1
0
Conversion time= 134 states (Max.)
1
Conversion time= 68 states (Max.)
Bit
Initial value
R/W
:
:
:
Содержание H8S/2631
Страница 28: ...xviii Appendix G Package Dimensions 1154 ...
Страница 341: ...316 Transfer SAR or DAR DAR or SAR Block area First block Nth block Figure 9 8 Memory Mapping in Block Transfer Mode ...
Страница 918: ...905 ø DREQ0 DREQ1 tDRQS tDRQH Figure 25 19 DMAC DREQ Input Timing ...
Страница 955: ...943 A 2 Instruction Codes Table A 2 shows the instruction codes ...