Hitachi H8S/2631, Руководство по оборудованию

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1013
TCSR0—Timer Control/Status Register 0
TCSR1—Timer Control/Status Register 1
TCSR2—Timer Control/Status Register 2
TCSR3—Timer Control/Status Register 3 H'FF6A
H'FF6B
H'FDC2
H'FDC3 TMR0
TMR1
TMR2
TMR3
7
CMFB
0
R/(W)
*
6
CMFA
0
R/(W)
*
5
OVF
0
R/(W)
*
4
—
1
—
3
OS3
0
R/W
0
OS0
0
R/W
2
OS2
0
R/W
1
OS1
0
R/W
TCSR1, TCSR3
7
CMFB
0
R/(W)
*
6
CMFA
0
R/(W)
*
5
OVF
0
R/(W)
*
4
—
0
R/W
3
OS3
0
R/W
0
OS0
0
R/W
2
OS2
0
R/W
1
OS1
0
R/W
Note: * Only 0 can be written to bits 7 to 5 ( to clear these flags).
TCSR2
7
CMFB
0
R/(W)
*
6
CMFA
0
R/(W)
*
5
OVF
0
R/(W)
*
4
ADTE
0
R/W
3
OS3
0
R/W
0
OS0
0
R/W
2
OS2
0
R/W
1
OS1
0
R/W
TCSR0
Bit 7: Compare match flag B
0 [Clearing]
(1) Reading CMFB then writing 0 to CMFB when CMFB=1
(2) When DTC is started by CMIB interrupt and DTC MRB DISEL bit is 0
[Setting]
When TCNT=TCORB 1
Bit 6: Compare match flag A
0 [Clearing]
(1) Reading CMFA then writing 0 to CMFA when CMFA=1
(2) When DTC is started by CMIA interrupt and DTC MRB DISEL bit is 0
[Setting]
When TCNT=TCORA 1
Bit 5: Timer overflow flag
0 [Clearing]
Reading OVF then writing 0 to OVF when OVF=1
[Setting]
When TCNT changes from H’FF to H’00 1
Bit 4: A/D trigger enable
0 A/D conversion start request by compare match A disabled
A/D conversion start request by compare match A enabled 1
Bits 3 to 0: Output select 3 to 0
No change at compare match B
0 output at compare match B
1 output at compare match B
Inverted output each compare match B (toggle output)
0
1
0
OS2 OS3
0 1
1
No change at compare match A
0 output at compare match A
1 output at compare match A
Inverted output each compare match A (toggle output)
0
1
0
OS0 OS1
0 1
1
Bit
Initial value
R/W
:
:
:
Bit
Initial value
R/W
:
:
:
Bit
Initial value
R/W
:
:
: