848
External Clock
Table 23-4 and figure 23-7 show the input conditions for the external clock.
Table 23-4 External Clock Input Conditions
V
CC
= 3.0 V
to 3.6 V,
PV
CC
= 3.0 V
to 5.5 V
V
CC
= 3.0 V
to 3.6 V
PV
CC
= 5.0 V
±10%
Item
Symbol
Min
Max
Min
Max
Unit
Test Conditions
External clock input low
pulse width
t
EXL
20
—
15
—
ns
Figure 23-7
External clock input
high pulse width
t
EXH
20
—
15
—
ns
External clock rise time t
EXr
—
10
—
5
ns
External clock fall time
t
EXf
—
10
—
5
ns
Clock low pulse
width level
t
CL
0.4
0.6
0.4
0.6
t
cyc
ø
≥
5 MHz
Figure
25-2
80
—
80
—
ns
ø < 5 MHz
Clock high pulse width
level
t
CH
0.4
0.6
0.4
0.6
t
cyc
ø
≥
5 MHz
80
—
80
—
ns
ø < 5 MHz
t
EXH
t
EXL
t
EXr
t
EXf
V
CC
×
0.5
EXTAL
Figure 23-7 External Clock Input Timing
Содержание H8S/2631
Страница 28: ...xviii Appendix G Package Dimensions 1154 ...
Страница 341: ...316 Transfer SAR or DAR DAR or SAR Block area First block Nth block Figure 9 8 Memory Mapping in Block Transfer Mode ...
Страница 918: ...905 ø DREQ0 DREQ1 tDRQS tDRQH Figure 25 19 DMAC DREQ Input Timing ...
Страница 955: ...943 A 2 Instruction Codes Table A 2 shows the instruction codes ...