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44
Type
Instruction
Size
*
1
Function
Arithmetic
operations
CLRMAC
—
0
→
MAC
Clears the multiply-accumulate register to zero.
LDMAC
STMAC
L
Rs
→
MAC, MAC
→
Rd
Transfers data between a general register and a
multiply-accumulate register.
Logic
operations
AND
B/W/L
Rd
∧
Rs
→
Rd, Rd
∧
#IMM
→
Rd
Performs a logical AND operation on a general register
and another general register or immediate data.
OR
B/W/L
Rd
∨
Rs
→
Rd, Rd
∨
#IMM
→
Rd
Performs a logical OR operation on a general register
and another general register or immediate data.
XOR
B/W/L
Rd
⊕
Rs
→
Rd, Rd
⊕
#IMM
→
Rd
Performs a logical exclusive OR operation on a general
register and another general register or immediate data.
NOT
B/W/L
¬ (Rd)
→
(Rd)
Takes the one's complement of general register
contents.
Shift
operations
SHAL
SHAR
B/W/L
Rd (shift)
→
Rd
Performs an arithmetic shift on general register contents.
1-bit or 2-bit shift is possible.
SHLL
SHLR
B/W/L
Rd (shift)
→
Rd
Performs a logical shift on general register contents.
1-bit or 2-bit shift is possible.
ROTL
ROTR
B/W/L
Rd (rotate)
→
Rd
Rotates general register contents.
1-bit or 2-bit rotation is possible.
ROTXL
ROTXR
B/W/L
Rd (rotate)
→
Rd
Rotates general register contents through the carry flag.
1-bit or 2-bit rotation is possible.
Bit-
manipulation
instructions
BSET
B
1
→
(<bit-No.> of <EAd>)
Sets a specified bit in a general register or memory
operand to 1. The bit number is specified by 3-bit
immediate data or the lower three bits of a general
register.
BCLR
B
0
→
(<bit-No.> of <EAd>)
Clears a specified bit in a general register or memory
operand to 0. The bit number is specified by 3-bit
immediate data or the lower three bits of a general
register.
BNOT
B
¬ (<bit-No.> of <EAd>)
→
(<bit-No.> of <EAd>)
Inverts a specified bit in a general register or memory
operand. The bit number is specified by 3-bit immediate
data or the lower three bits of a general register.
Содержание H8S/2631
Страница 28: ...xviii Appendix G Package Dimensions 1154 ...
Страница 341: ...316 Transfer SAR or DAR DAR or SAR Block area First block Nth block Figure 9 8 Memory Mapping in Block Transfer Mode ...
Страница 918: ...905 ø DREQ0 DREQ1 tDRQS tDRQH Figure 25 19 DMAC DREQ Input Timing ...
Страница 955: ...943 A 2 Instruction Codes Table A 2 shows the instruction codes ...