421
Bit 7
Bit 6
Bit 5
Bit 4
Channel
IOD3 IOD2 IOD1 IOD0 Description
0
0
0
0
0
TGR0D is Output disabled
(Initial value)
1
1
0
1
output
compare
register
*
2
Initial output is 0
output
0 output at compare match
1 output at compare match
Toggle output at compare
match
1
0
0
Output disabled
1
Initial output is 1
0 output at compare match
1
0
output
1 output at compare match
1
Toggle output at compare
match
1
0
0
1
0
1
*
TGR0D is
input
capture
register
*
2
Capture input
source is
TIOCD0 pin
Input capture at rising edge
Input capture at falling edge
Input capture at both edges
1
*
*
Capture input
source is channel
1/count clock
Input capture at TCNT1
count-up/count-down
*
1
*
: Don’t care
Notes: 1. When bits TPSC2 to TPSC0 in TCR1 are set to B'000 and ø/1 is used as the TCNT1
count clock, this setting is invalid and input capture is not generated.
2. When the BFB bit in TMDR0 is set to 1 and TGR0D is used as a buffer register, this
setting is invalid and input capture/output compare is not generated.
Содержание H8S/2631
Страница 28: ...xviii Appendix G Package Dimensions 1154 ...
Страница 341: ...316 Transfer SAR or DAR DAR or SAR Block area First block Nth block Figure 9 8 Memory Mapping in Block Transfer Mode ...
Страница 918: ...905 ø DREQ0 DREQ1 tDRQS tDRQH Figure 25 19 DMAC DREQ Input Timing ...
Страница 955: ...943 A 2 Instruction Codes Table A 2 shows the instruction codes ...