145
Bit 3—DACK Timing Select (DDS): When using the DRAM interface, this bit selects the
DMAC single address transfer bus timing.
Bit 3
DDS
Description
0
When performing DMAC single address transfers to DRAM, always execute full
access. The
DACK
signal is output as a low-level signal from the T
r
or T
1
cycle.
1
Burst access is also possible when performing DMAC single address
tranfers to DRAM. The
DACK
signal is output as a low-level signal
from the T
C1
or T
2
cycle.
(Initial value)
Bit 2—Read CAS Timing Select (RCTS): Selects the
CAS
signal output timing.
Bit 2
RCTS
Description
0
CAS
signal output timing is same when reading and writing.
(Initial value)
1
When reading,
CAS
signal is asserted half cycle earlier than when writing.
Bit 1—Write Data Buffer Enable (WDBE): This bit selects whether or not to use the write
buffer function in the external write cycle or the DMAC single address cycle.
Bit 1
WDBE
Description
0
Write data buffer function not used
(Initial value)
1
Write data buffer function used
Bit 0—WAIT Pin Enable (WAITE): Selects enabling or disabling of wait input by the
WAIT
pin.
Bit 0
WAITE
Description
0
Wait input by
WAIT
pin disabled.
WAIT
pin can be used as I/O port.
(Initial value)
1
Wait input by
WAIT
pin enabled
Содержание H8S/2631
Страница 28: ...xviii Appendix G Package Dimensions 1154 ...
Страница 341: ...316 Transfer SAR or DAR DAR or SAR Block area First block Nth block Figure 9 8 Memory Mapping in Block Transfer Mode ...
Страница 918: ...905 ø DREQ0 DREQ1 tDRQS tDRQH Figure 25 19 DMAC DREQ Input Timing ...
Страница 955: ...943 A 2 Instruction Codes Table A 2 shows the instruction codes ...